• Journal of Advanced Navigation Technology
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• v.21 no.6
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• pp.659-665
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• 2017

In this paper, a low complexity fast Fourier transform(FFT) processor is proposed for multiple input multiple output(MIMO) systems. The IEEE 802.11ac standard has been adopted along with the demand for a system capable of high channel capacity and Gbps transmission in order to utilize various multimedia services using a wireless LAN. The proposed scalable FFT processor can support the variable length of 64, 128, 256, and 512 for 8x8 antenna configuration as specified in IEEE 802.11ac standard with MIMO-OFDM scheme. By reducing the required number of non-trivial multipliers with mixed-radix(MR) and multipath delay commutator(MDC) architecture, the complexity of the proposed FFT processor was dramatically decreased. Implementation results show that the proposed FFT processor can reduced the logic gate count by 50%, compared with the radix-2 SDF FFT processor. Also, compared with the 8-channel MR-2/2/2/4/2/4/2 MDC processor and 8-channel MR-2/2/2/8/8 MDC processor, it is shown that the gate count is reduced by 18% and 17% respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1263-1270
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• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.64-72
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• 2012

Synchronization including timing recovery, frequency offset compensation, and frame synchronization is most important signal processing block in all wireless/wired communication systems. In most communication systems, synchronization schemes based on training sequences or preambles are used. WLAN standards of 802.11a/g/n released by IEEE are based on OFDM systems. OFDM systems are known to be much more sensitive to frequency and timing synchronization errors than single carrier systems. A loss of orthogonality between the multiplexed subcarriers can result in severe performance degradations. The starting position of the frame and the beginning of the symbol and training symbol can be estimated using correlation methods. Correlation processing functionality is usually complex because of large number of multipliers in implementation especially when the reference signal is non-binary. In this paper, a simple correlation based synchronization scheme is proposed for IEEE 802.11a/g/n systems. Existing property of a periodicity in the training symbols are exploited. Simulation and implementation results show that the proposed method has much smaller complexity without any performance degradation than the existing schemes.

• Journal of IKEEE
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• v.17 no.4
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• pp.570-578
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• 2013

This paper proposed an $8{\times}8$ HEVC inverse core transform architecture reusing multipliers. In HEVC core transform, processing of lower size block is identical with even part of upper size block. So an $8{\times}8$ core transform architecture can process both $8{\times}8$ and $4{\times}4$ core transforms. However, when $8{\times}8$ core transform architecture is exploited, frame processing time doubles in $4{\times}4$ core transform, since $8{\times}8$ and $4{\times}4$ core transforms concurrently process 8 and 4 pixels, respectively. In this paper, a novel inverse core transform architecture is proposed based on multiplier reuse. It runs as an $8{\times}8$ inverse core transformer or two $4{\times}4$ inverse core transformer. Its frame processing time is same in $8{\times}8$ and $4{\times}4$ core transforms, and reduces gate counts by 12%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2015-2024
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• 1999

Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.37 no.1
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• pp.9-18
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• 2013

Two-phase vapor-liquid flows exist in many shell and tube heat exchangers such as condensers, evaporators, and nuclear steam generators. To understand the fluid dynamic forces acting on a structure subjected to a two-phase flow, it is essential to obtain detailed information about the characteristics of a two-phase flow. The characteristics of a two-phase flow and the flow parameters were introduced, and then, an experiment was performed to evaluate the pressure loss in the tube bundles and the fluid-dynamic force acting on the cylinder owing to the pressure distribution. A two-phase flow was pre-mixed at the entrance of the test section, and the experiments were undertaken using a normal triangular array of cylinders subjected to a two-phase cross-flow. The pressure loss along the flow direction in the tube bundles was measured to calculate the two-phase friction multiplier, and the multiplier was compared with the analytical value. Furthermore, the circular distributions of the pressure on the cylinders were measured. Based on the distribution and the fundamental theory of two-phase flow, the effects of the void fraction and mass flux per unit area on the pressure coefficient and the drag coefficient were evaluated. The drag coefficient was calculated by integrating the measured pressure on the tube by a numerical method. It was found that for low mass fluxes, the measured two-phase friction multipliers agree well with the analytical results, and good agreement for the effect of the void fraction on the drag coefficients, as calculated by the measured pressure distributions, is shown qualitatively, as compared to the existing experimental results.

• Journal of Radiation Protection and Research
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• v.30 no.2
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• pp.69-75
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• 2005

Gas avalanche microdetectors, such as micro-strip gas chamber (MSGC), micro-gap chamber (MGC), micro-dot chamber (MDOT), etc., are operated under high voltage to induce large electron avalanche signal around micro-size anodes. Therefore, the anodes are highly exposed to electrical damage, for example, sparking because of the interaction between high electric field strength and charge multiplication around the anodes. Gas electron multiplier (GEM) is a charge preamplifying device in which charge multiplication can be confined, so that it makes that the charge multiplication region can be separate from the readout micro-anodes in 9as avalanche microdetectors possible. Primary electron collection efficiency is an important measure for the GEM performance. We have defined that the primary electron collection efficiency is the fractional number of electron trajectories reaching to the collection plane from the drift plane through the GEM holes. The electron trajectories were estimated based on 3-dimensional (3D) finite element method (FEM). In this paper, we present the primary electron collection efficiency with respect to various GEM operation parameters. This simulation work will be very useful for the better design of the GEM.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.36-42
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• 2010

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically $log_2N$) as the FFT point-size (N) increases, the number of required registers (or, memories) increases linearly. In large point-size FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 38.5% area reduction compared with previous IFFT designs.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.43-51
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• 2008

In this paper, we are implemented low-power structure for Inter prediction, Intra prediction, Deblocking filter, Transform and Quantization blocks in H.264/AVC Encoder. The proposed Inter/Intra prediction blocks are shown 60.2% cell area reduction by adder reduction through Distributed Arithmetic, 44.3% add operation reduction using MUX for hardware share in Deblocking filter block. Furthermore we applied CSD and CSS process to reduce the cell area instead of multipliers that take a lot of area. The FPGA(Field Programmable Gate Array) and ARM Process based H.264/AVC encoder is implemented using proposed low power IPs. The proposed structure Platforms are implemented to interlock with FPGA and ARM processors. H.264/AVC Encoder implementation using Platforms shows that proposed low-power IPs can use H.264/AVC Encoder SoC effectively.

• Journal of Korea Water Resources Association
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• v.46 no.11
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• pp.1041-1052
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• 2013

In this study, we estimate parameters of a distributed hydrologic model, GRM (grid based rainfall-runoff model), using a model-independent parameter estimation tool, PEST. We implement auto calibration of model parameters such as initial soil moisture, multipliers of overland roughness and soil hydraulic conductivity in the Geumho River Catchment and the Gamcheon Catchment using radar rainfall estimates and ground-observed rainfall represented by Thiessen interpolation. Automatic calibration is performed by GRM-MP (multiple projects), a modified version of GRM without GUI (graphic user interface) implementation, and "Parallel PEST" to improve estimation efficiency. Although ground rainfall shows similar or higher cumulative amount compared to radar rainfall in the areal average, high spatial variation is found only in radar rainfall. In terms of accuracy of hydrologic simulations, radar rainfall is equivalent or superior to ground rainfall. In the case of radar rainfall, the estimated multiplier of soil hydraulic conductivity is lower than 1, which may be affected by high rainfall intensity of radar rainfall. Other parameters such as initial soil moisture and the multiplier of overland roughness do not show consistent trends in the calibration results. Overall, calibrated parameters show different patterns in radar and ground rainfall, which should be carefully considered in the rainfall-runoff modelling applications using radar rainfall.