• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.678-684
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• 2015

Near-threshold computing (NTC) is now regarded as a promising candidate for innovative power reduction, which cannot be achieved with conventional super-threshold computing (STC). However, performance degradation and vulnerability to process variation in the NTC regime are the primary concerns. In this paper, we propose a voltage- and frequency-tuning methodology for mitigating the process-variation-induced problems in NTC-based manycore architectures. To implement the proposed methodology, we build up multiple-voltage multiple-frequency (MVMF) islands and apply a voltage-frequency tuning algorithm based on the critical-path monitoring technique to reduce the effects of process variation and maximize energy efficiency in the post-silicon stage. Experimental results show that the proposed methodology reduces overall power consumption by 8.2-20.0%, compared to existing methods in variation-sensitive NTC environments.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.1112-1115
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• 1990

Described is a new control signal transmission system which utilizes an optical fiber to transmit 2-bit control signals from the transmitter to receiver. In the transmitter the DC series control voltages are converted into the multiple frequency signals by voltage controlled oscillator (VCO). The multiple frequency signals can easily be transmitted by optical fiber. In the receiver the multiple frequency signals can be detected by analog or digital circuits and then be converted into 2-state control signals which can be used for a variety of applications.

• Journal of Power Electronics
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• v.17 no.4
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• pp.972-982
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• 2017

The Park's vector of stator current is a popular technique for the detection of induction motor faults. While the detection of the faulty condition using the Park's vector technique is easy, the classification of different types of faults is intricate. This problem is overcome by the Multiple Park's Vector (MPV) approach proposed in this paper. In this technique, the characteristic fault frequency component (CFFC) of stator winding faults, rotor winding faults, unbalanced voltage and bearing faults are extracted from three phase stator currents. Due to constructional asymmetry, under the healthy condition these characteristic fault frequency components are unbalanced. In order to balanced them, a correction factor is added to the characteristic fault frequency components of three phase stator currents. Therefore, the Park's vector pattern under the healthy condition is circular in shape. This pattern is considered as a reference pattern under the healthy condition. According to the fault condition, the amplitude and phase of characteristic faults frequency components changes. Thus, the pattern of the Park's vector changes. By monitoring the variation in multiple Park's vector patterns, the type of fault and its severity level is identified. In the proposed technique, the diagnosis of faults is immune to the effects of unbalanced voltage and multiple faults. This technique is verified on a 7.5 hp three phase wound rotor induction motor (WRIM). The experimental analysis is verified by simulation results.

• International Journal of Control, Automation, and Systems
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• v.6 no.4
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• pp.613-619
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• 2008

A method to produce a desired current pattern in a multiple-source EIT system using voltage sources is presented. Application of current patterns to a body is known to be superior to the application of voltage patterns in terms of high spatial frequency noise suppression, resulting in high accuracy in conductivity and permittivity images. Since current sources are difficult and expensive to build, the use of voltage sources to apply the current pattern is desirable. An iterative algorithm presented in this paper generates the necessary voltage pattern that will produce the desired current pattern. The convergence of the algorithm is shown under the condition that the estimation error of the linear mapping matrix from voltage to current is small. Simulation results are presented to illustrate the convergence of the output current.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.1
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• pp.1-6
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• 2019

An extremely small size multi-loop phase-locked loop(PLL) keeping phase noise performances has been proposed. It has been designed to have the loop filter made of small single capacitor with multiple Frequency Voltage Converters (FVCs) because the main goal is to make the size of the proposed PLL extremely small. Multiple FVCs which are connected to voltage controlled oscillator(VCO) make multiple negative feedback loops in PLL. Those multiple negative feedback loops enable the PLL with the loop filter made of an extremely small size single capacitor operate stably. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the 1.6ps jitter and $10{\mu}s$ locking time.

• Journal of Power Electronics
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• v.8 no.4
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• pp.332-344
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• 2008

High frequency AC (HFAC) power distribution systems delivering power through a high frequency AC link with sinusoidal voltage have the advantages of simple structure and high efficiency. In a multiple module system, where multiple resonant inverters are paralleled to the high frequency AC bus through connection inductors, it is necessary for the output voltage phase angles of the inverters be controlled so that the circulating current among the inverters be minimized. However, the phase angle of the resonant inverters output voltage can not be controlled with conventional phase shift modulation or pulse width modulation. The phase angle is a function of both the phase of the gating signals and the impedance of the resonant tank. In this paper, we proposed a pulse phase modulation (PPM) concept for the resonant inverters, so that the phase angle of the output voltage can be regulated. The PPM can be used to minimize the circulating current between the resonant inverters. The mechanisms of the phase angle control and the PPM were explained. The small signal model of a PPM controlled half-bridge resonant inverter was analyzed. The concept was verified in a half bridge resonant inverter with a series-parallel resonant tank. An HFAC power distribution system with two resonant inverters connected in parallel to a 500kHz, 28V AC bus was presented to demonstrate the applicability of the concept in a high frequency power distribution system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.9-17
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• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.331-333
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• 2004

In this study, we implement the multiple frequency bioelectrical impedance analysis system for body composition analysis. Overall system consists of : 1) conductivity electrodes to contact with hands and foots, 2) multiple frequency alternating current signal generator for generating 5, 50, 250kHz frequency and 800uA contained alternating current signal, 3) voltage signal detector, 4) phase signal detector, 5) key-pad to input individual information, 6) micro controller for data processing, 7) LCD for processed data to display, 8) system power, We explain the architecture of the system and required theory to implement the system. Finally, experimental results are illustrated to show the performance of the system.

• Journal of Power Electronics
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• v.14 no.1
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• pp.165-174
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• 2014

The cascaded H-Bridge Dynamic Voltage Restorer (DVR) is used for protecting high voltage and large capacity loads from voltage sags. The LC filter in the DVR is needed to eliminate switching ripples, which also provides an accurate tracking feature in a certain frequency range. Therefore, the parameter optimization of the LC filter is especially important. In this paper, the value range functions for the inductance and capacitance in LC filters are discussed. Then, parameter variations under different conditions of voltage sags and power factors are analyzed. In addition, an optimized design method is also proposed with the consideration of multiple impact factors. A detailed optimization procedure is presented, and its validity is demonstrated by simulation and experimental results. Both results show that the proposed method can improve the LC filter design for a cascaded H-Bridge DVR and enhance the performance of the whole system.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.207-210
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• 2002

This paper describes a design of multiple-mode single-output DC/DC converter which can be used in both up and down conversion. Proposed up/down converter does not produce a negative voltage which is generated in conventional buck-boost type converter. Three types of operation mode(up/down/bypass) are controlled by the input voltage sense and command signals of target output voltage. PFM(pulse frequency modulation) control is adopted and modified for fast tracking and for precise output voltage level with an aid of output voltage sense. Designed DC/DC converter has the performance of less than 5 % ripple and higher than 80 % efficiency. Chip area is 3.50 mm ${\times}$ 2.05 mm with standard 0.35 $\mu\textrm{m}$ CMOS technology.