• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.10
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• pp.78-88
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• 1990

To evaluate the performance of a multiprocessor system, a discrete event model of memory interference in the system employing multiple-bus interconnection networks is proposed. An analytic model of the system is presented and then simulator models are implemented for cross-verifying the analytic results and simulation results. The simulator model takes as input the number of processors, the number of memory modules, the number of buses and the local memory miss ratio. The model produces as output the memory bandwidth, the processor, memory module and bus utilization and the bus contention ratio. Using the model in the design of the system, it is possible to evaluate the system performance by analyzing the interaction of the input parameters.

• Journal of Information Processing Systems
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• v.15 no.1
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• pp.151-158
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• 2019

With the recent advances of memory technologies, high-performance non-volatile memories such as non-volatile dual in-line memory module (NVDIMM) have begun to be used as an addition or an alternative to server-side storages. When these memory bus-connected storages (MBSs) are installed over non-uniform memory access (NUMA) servers, the distance between NUMA nodes and MBSs is one of the crucial factors that influence file processing performance, because the access latency of a NUMA system varies depending on its distance from the NUMA nodes. This paper presents the design and implementation of a high-performance logical volume manager for MBSs, called MBS-LVM, when multiple MBSs are scattered over a NUMA server. The MBS-LVM consolidates the address space of each MBS into a single global address space and dynamically utilizes storage spaces such that each thread can access an MBS with the lowest latency possible. We implemented the MBS-LVM in the Linux kernel and evaluated its performance by porting it over the tmpfs, a memory-based file system widely used in Linux. The results of the benchmarking show that the write performance of the tmpfs using MBS-LVM has been improved by up to twenty times against the original tmpfs over a NUMA server with four nodes.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.12
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• pp.2131-2134
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• 2010

In this paper, the on-line system schemes for coordinated control system of multiple FACTS were presented to enhance the voltage stability around the metropolitan areas. In order to coordinated control system of FACTS devices, MFC on-line system calculates the optimal set point(Vref, Qrev) of FACTS devices using the coordinated control algorithm with real time network data which is transferred from SCADA/EMS system. If the system is unstable after contingencies, the new operation set-point of FACTS would be determined using bus sensitivity from tangent vector at voltage instability point. Otherwise, we would determine the new operation set-point of FACTS for considering economical operation, like as active power loss minimization using Optimal Power Flow algorithm. As the test, MFC(Multiple FACTS Coordinated control) on-line system will be installed in Korea power system.

• Journal of the Semiconductor & Display Technology
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• v.8 no.2
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• pp.37-42
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• 2009

This paper presents an idea of implementation of many semiconductor equipments. The idea is a new design methodology of the Networked Control Systems (NCSs) using CAN (Controller Area Network) will be discussed. The Distributed Control Systems (DCSs) is very useful to control multiple systems that have a distance to communicate. The CAN protocol is very strong to noise, also provides the user with many powerful functionality. Only one communication line (BUS) is used, so that a control and a maintenance of those systems are very easy. This paper is concerned with the speed control of multiple DC motors using CAN Protocol. Experimental systems are made to validate effectiveness of the systems. The results of the experiment show that the NCSs using CAN has excellency in real time control.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.5_6
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• pp.257-266
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• 2007

In On-Chip bus, the arbitration scheme is one of the critical factors that decide the overall system performance. The arbitration scheme used in traditional shared bus is the master-side arbitration based on the request and grant signals between multiple masters and single arbiter. In the case of the master-side arbitration, only one master and one slave can transfer the data at a time. Therefore the throughput of total bus system and the utilization of resources are decreased in the master-side arbitration. However in the slave-side arbitration, there is an arbiter at each slave port and the master just starts a transaction and waits for the slave response to proceed to the next transfer. Thus, the unit of arbitration can be a transaction or a transfer. Besides the throughput of total bus system and the utilization of resources are increased since the multiple masters can simultaneously perform transfers with independent slaves. In this paper, we implement and analyze the arbitration schemes for the Multi-Layer AHB BusMatrix based on the slave-side arbitration. We implement the slave-side arbitration schemes based on fixed priority, round robin and dynamic priority and accomplish the performance simulation to compare and analyze the performance of each arbitration scheme according to the characteristics of the master and slave. With the performance simulation, we observed that when there are few masters on critical path in a bus system, the arbitration scheme based on dynamic priority shows the maximum performance and in other cases, the arbitration scheme based on round robin shows the highest performance. In addition, the arbitration scheme with transaction based multiplexing shows higher performance than the same arbitration scheme with single transfer based switching in an application with frequent accesses to the long latency devices or memories such as SDRAM. The improvements of the arbitration scheme with transaction based multiplexing are 26%, 42% and 51%, respectively when the latency times of SDRAM are 1, 2 and 3 clock cycles.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1957-1958
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the simulator and algorithm that judges whether Tri-state Bus lines is the circuit which have X-value or One-hot Value after presuming the control signal of the lines which output X-value in the logic circuit to solve the most serious problems.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.396-398
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• 2003

This paper presents the scheme for load model based dispersed generation system (DGs) installation and operation in unbalanced distribution systems. Groups of each individual load model consist of residential, industrial, commercial, official and agricultural load. The main idea of solving fuzzy nonlinear goal programming is to transform the original objective function and constraints into the equivalent multiple objective functions with fuzzy sets to evaluate their imprecise nature for the criterion of power loss minimization, the number or total capacity of DGs and the bus voltage deviation, and then solve the problem using genetic algorithms. The method proposed was applied to IEEE 13 bus test systems to demonstrate its effectiveness.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.2
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• pp.148-159
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• 1987

This paper proposes CSMA/CD-TDM/SD(carrier sense multiple access/collision detection-time division multiplexing/silence detection) control scheme in bus type integrated data/voice local area networks. Simulation results show that this control scheme satisfies the lossless real-time constraints of the voice traffic and improves the data throughput-delay characteristics as compared to those of the CSMA/CD/MPD and the CSMA/CD-TDMA.

• Journal of Power Electronics
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• v.12 no.5
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• pp.830-841
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• 2012

Active power filters (APF) can be employed for harmonic compensation in power systems. In this paper, a fuzzy based method is proposed for identification of probable APF nodes of a radial distribution system. The modified adaptive particle swarm optimization (MAPSO) technique is used for final selection of the APFs size. A combination of Fuzzy-MAPSO method is implemented to determine the optimal allocation and size of APFs. New fuzzy membership functions are formulated where the harmonic current membership is an exponential function of the nodal injecting harmonic current. Harmonic voltage membership has been formulated as a function of the node harmonic voltage. The product operator shows better performance than the AND operator because all harmonics are considered in computing membership function. For evaluating the proposed method, it has been applied to the 5-bus and 18-bus test systems, respectively, which the results appear satisfactorily. The proposed membership functions are new at the APF placement problem so that weighting factors can be changed proportional to objective function.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.188-198
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• 2013

In order to increase its performance, NAND flash memory-based storage is composed of data buses that are shared by a number of flash memories and uses a parallel technique that can carry out multiple flash memory operations simultaneously. Since the storage performance is strongly influenced by the performance of each data bus, it is important to improve the utilization of the bus by ensuring effective scheduling of operations by the storage controller. However, this is difficult because of dynamic changes in buses due to the unique characteristics of each operation with different timing, cost, and usage by each bus. Furthermore, the scheduling technique for increasing bus utilization may cause unanticipated operation delay and wastage of storage resource. In this study, we suggest various dynamic operation scheduling techniques that consider data bus performance and storage resource efficiency. The proposed techniques divide each operation into three different stages and schedule each stage depending on the characteristics of the operation and the dynamic status of the data bus. We applied the suggested techniques to the controller and verified them on the FPGA platform, and found that program operation decreased by 1.9% in comparison to that achieved by a static scheduling technique, and bus utilization and throughput was approximately 4-7% and 4-19% higher, respectively.