• Journal of Practical Agriculture & Fisheries Research
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• v.13 no.1
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• pp.3-17
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• 2011

Pipelines of processor have been growing deeper and issue widths wider over the years. If this trend continues, branch misprediction penalty will become very high. Branch misprediction is the single most significant performance limiter for improving processor performance using deeper pipelining. Therefore, more accurate branch predictor becomes an essential part of modem processors for FAFF(Food, Agriculture, Forestry, Fisheries)Information Processing. In this paper, we propose a branch prediction mechanism, using variable length history, which predicts using a bank having higher prediction accuracy among predictions from five banks. Bank 0 is a bimodal predictor which is indexed with the 12 least significant bits of the branch PC. Banks 1,2,3 and 4 are predictors which are indexed with different global history bits and the branch PC. In simulation results, the proposed mechanism outperforms gshare predictors using fixed history length of 12 and 13, up to 6.34% in prediction accuracy. Furthermore, the proposed mechanism outperforms gshare predictors using best history lengths for benchmarks, up to 2.3% in prediction accuracy.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.1
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• pp.33-40
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• 2007

Processor pipelines have been growing deeper and issue widths wider over the years. If this trend continues, the branch misprediction penalty will become very high. Branch misprediction is the single most significant performance limiter for improving processor performance using deeper pipelining. Therefore, more accurate branch predictor becomes an essential part of modern processors. Several branch predictors combine a part of the branch address with a fixed amount of global branch history to make a prediction. These predictors cannot perform uniformly well across all programs because the best amount of branch history to be used depends on the program and branches in the program. Therefore, predictors that use a fixed history length are unable to perform up to their potential performance. In this paper, we propose a branch prediction mechanism, using variable length history, which predicts using a bank having higher prediction accuracy among predictions from five banks. Bank 0 is a bimodal predictor which is indexed with the 12 least significant bits of the branch address. Banks 1, 2, 3 and 4 are predictors which are indexed with different global history bits and the branch PC. In simulation results, the proposed mechanism outperforms gshare predictors using fixed history length of 12 and 13 , up to 6.34% in prediction accuracy. Furthermore, the proposed mechanism outperforms gshare predictors using best history lengths for benchmarks, up to 2.3% in prediction accuracy.

• Journal of the Korea Society of Computer and Information
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• v.8 no.3
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• pp.40-46
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• 2003

The high-performance processors have recently employed sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. For the query processing of database management systems, those hardware characteristics are the important research issue. The latest works show that the cache miss penalty between main memory and CPU becomes new bottlenecks and the branch misprediction causes serious resource-waste. An effcient algorithm for query processing of aggregate functions considering these hardware characteristics was proposed in this dissertation.

• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1652-1659
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• 1998

To provide performance gains by reducing the operand referencing latency and data cache bandwidth requirements, we present an operand reference prediction cache (ORPC) which predicts operand value and address translation during the instruction fetch stage. The prediction is verified in the early stage, and thus it minimizes the performance penalty caused by the misprediction. Through the trace-driven simulation of six benchmark programs, the performance improvement by proposed three aRPC stmctures (OfiPC1, OfiPC2. ORPC3)is analysed and validated.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.11
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• pp.592-600
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• 2001

To improve the performance of wide-issue Superscalar microprocessors, it is essential to increase the width of instruction fetch and issue rate. Data dependences are major hurdle to exploit ILP(Instruction-Level Parallelism) efficiently, so several related works have suggested that the limits imposed by data dependences can be overcome to some extent with the use of the data value prediction. But the suggested mechanisms may access the same value prediction table entry again before they have been updated with a real data value. They will cause incorrect value prediction by using stable data and incur misprediction penalty and lowering performance. In this paper, we propose a new hybrid value predictor which achieve high performance by reducing stale data. Because the proposed hybrid value predictor can update the prediction table speculatively, it efficiently reduces the number of mispredicted instruction due to stable due to stale data. For SPECint95 benchmark programs on the 16-issue superscalar processors, simulation results show that the average prediction accuracy increase from 59% for non-speculative update to 72% for speculative update.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.1
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• pp.9-26
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• 2005

In the pursuit of ever higher levels of performance, recent computer systems have made use of deep pipeline, dynamic scheduling and multi-issue superscalar processor technologies. In this situations, branch prediction schemes are an essential part of modem microarchitectures because the penalty for a branch misprediction increases as pipelines deepen and the number of instructions issued per cycle increases. In this paper, we propose a novel branch prediction scheme, direction-gshare(d-gshare), to improve the prediction accuracy. At first, we model a neural network with the components that possibly affect the branch prediction accuracy, and analyze the variation of their weights based on the neural network information. Then, we newly add the component that has a high weight value to an original gshare scheme. We simulate our branch prediction scheme using Simple Scalar, a powerful event-driven simulator, and analyze the simulation results. Our results show that, compared to bimodal, two-level adaptive and gshare predictor, direction-gshare predictor(d-gshare. 3) outperforms, without additional hardware costs, by up to 4.1% and 1.5% in average for the default mont of embedded direction, and 11.8% in maximum and 3.7% in average for the optimal one.