• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.43-55
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• 2003

As the development of If industries and their electronic device manufacturing technology have been accelerated recently, the request for electronic devices with small size, light weight, and high performance has been inducing that electronic package and substrate (PCB) companies have to develop substrates with low cost, high dense I/O, excellent thermal properties and electrical properties. Therefore, world-wide chip makers have been setting their own severe reliability standards and requiring their suppliers to keep specification and to develop green, high frequency and high-performing substrates. Because properties of substrates are dependent mainly on their constituent materials, the application of them showing superior properties is expected to satisfy the customer's requirement. Therefore, substrate companies should ensure the superiority of materials and assure their competitive capability of substrates by analyzing the latest trends of technology and properties of the materials.

• Journal of the Korean Ceramic Society
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• v.53 no.3
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• pp.263-272
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• 2016

Electronic structure calculations have become a powerful foundation for computational materials engineering. Four major factors have enabled this unprecedented evolution, namely (i) the development of density functional theory (DFT), (ii) the creation of highly efficient computer programs to solve the Kohn-Sham equations, (iii) the integration of these programs into productivity-oriented computational environments, and (iv) the phenomenal increase of computing power. In this context, we describe recent applications of the Vienna Ab-initio Simulation Package (VASP) within the MedeA$^{(R)}$ computational environment, which provides interoperability with a comprehensive range of modeling and simulation tools. The focus is on technological applications including microelectronic materials, Li-ion batteries, high-performance ceramics, silicon carbide, and Zr alloys for nuclear power generation. A discussion of current trends including high-throughput calculations concludes this article.

• Korean Journal of Materials Research
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• v.9 no.11
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• pp.1095-1101
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• 1999

Electroless Ni plating is applied to form bumps and UBM layer for flip chip interconnection. Characteristics of electroless Ni are also investigated. Zincate pretreatment is analyzed and plated layer characteristics are investigated according to variables like temperature, pH and heat treatment. Based on these observations, characteristics dependence to each variables and optimum electroless Ni plating conditions for flip-chip interconnection are suggested. Electroless Ni has 10wt% P, $60\mu\Omega$-cm resistivity, 500HV hardness and amorphous structure. It changes crystallized structure and hardness increases after heat treatment After interconnection of electroless Ni bumps by ACF flip chip method, we show their advantages and possibility in microelectronic package applications.

• Corrosion Science and Technology
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• v.6 no.2
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• pp.50-55
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• 2007

The smaller size and higher integration of advanced electronic package systems result in severe electrochemical reliability issues in microelectronic packaging due to higher electric field under high temperature and humidity conditions. Under these harsh conditions, electronic components respond to applied voltages by electrochemical ionization of metal and the formation of a filament, which leads to short-circuit failure of an electronic component, which is termed electrochemical migration. This work aims to evaluate electrochemical migration susceptibility of the pure Sn, Sn-3.5Ag, Sn-3.0Ag-0.5Cu solder alloys in $Na_{2}SO_{4}$. The water drop test was performed to understand the failure mechanism in a pad patterned solder alloy. The polarization test and anodic dissolution test were performed, and ionic species and concentration were analyzed. Ag and Cu additions increased the time to failure of Pb-free solder in 0.001 wt% $Na_{2}SO_{4}$ solution at room temperature and the dendrite was mainly composed of Sn regardless of the solders. In the case of SnAg solders, when Ag and Cu added to the solders, Ag and Cu improved the passivation behavior and pitting corrosion resistance and formed inert intermetallic compounds and thus the dissolution of Ag and Cu was suppressed; only Sn was dissolved. If ionic species is mainly Sn ion, dissolution content than cathodic deposition efficiency will affect the composition of the dendrite. Therefore, Ag and Cu additions improve the electrochemical migration resistance of SnAg and SnAgCu solders.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.6
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• pp.3442-3447
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• 2014

A simple method to evaluate the hygroscopic characteristics of polymer of microelectronic plastic package is suggested. To evaluate the characteristics, specimens were prepared, and the internally absorbed moisture masses were measured as a function of the absorbing time and calculated numerically. The hygroscopic pressure ratio was calculated by heat transfer analysis supported by commercial FEM code because the hygroscopic diffusion equation has the same form as the heat transfer equation. The moisture masses were then summed by the self developed code. The nonconductive polymers had quite different characteristics for the different lots, even though they were the same products. The absorbed moisture mass variations were calculated for several different characteristics, and the optimal curve of the mass variation close to experimental data was selected, whose solubility and diffusivity were affected by the hygroscopic characteristics of the material. The method can be useful in the industrial fields to quickly characterize the polymer material of the semiconductor package because the fast correspondence is normally required in industry. The weight changes in the aluminum-nonconductive-polymer joint due to moisture absorption were measured. The deformed system was also measured using the Moire Interferometry system and compared with the results of finite element analysis.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.3 s.40
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• pp.1-8
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• 2006

Higher density integration and adoption of new materials in advanced electronic package systems result in severe electrochemical reliability issues in microelectronic packaging due to higher electric field under high temperature and humidity conditions. Under these harsh conditions, metal interconnects respond to applied voltages by electrochemical ionization and conductive filament formation, which leads to short-circuit failure of the electronic package. In this work, in-situ water drop test and evaluation of corrosion characteristics for SnPb solder alloys in D.I. water and NaCl solutions were carried out to understand the fundamental electrochemical migration characteristics and to correlate each other. It was revealed that electrochemical migration behavior of SnPb solder alloys was closely related to the corrosion characteristics, and Pb was primarily ionized in both D.I. water and $Cl^{-}$ solutions. The quality of passive film formed at film surface seems to be critical not only for corrosion resistance but also for ECM resistance of solder alloys.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.79-84
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• 2016

A flexible electronic device deformed by external force causes the failure of a semiconductor die. Even without failure, the repeated elastic deformation changes carrier mobility in the channel and increases resistivity in the interconnection, which causes malfunction of the integrated circuits. Therefore it is desirable that a semiconductor die be placed on a neutral line where the mechanical stress is zero. In the present study, we investigated the effects of design factors on the position of neutral line by finite element analysis (FEA), and expected the possible failure behavior in a flexible face-down packaging system assuming flip-chip bonding of a silicon die. The thickness and material of the flexible substrate and the thickness of a silicon die were considered as design factors. The thickness of a flexible substrate was the most important factor for controlling the position of the neutral line. A three-dimensional FEA result showed that the von Mises stress higher than yield stress would be applied to copper bumps between a silicon die and a flexible substrate. Finally, we suggested a designing strategy for reducing the stress of a silicon die and copper bumps of a flexible face-down packaging system.

• Polymer(Korea)
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• v.30 no.6
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• pp.519-524
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• 2006

Poly(4-vinyl pyridine) (PVP) and its copolymers, poly(4-vinyl pvridine- co-acrylamide) and poly(4-vinyl pyridine-co-allylamine), were synthesized and evaluated for application to organic solder-ability preservatives (OSP). The copolymers were synthesized by radical polymerization of vinyl pyridine in the presence of acrylamide or allylamine as a comonomer. Various kinds of polymers with different chemical composition were synthesized by varying the feed ratio of monomers and their low $M_w$ polymers can be obtained by adding 2-mercaptoethanol as a chain transfer agent during poly-merization. All the polymers showed good adhesion properties on Cu pad when they were spin-coated. Especially, allylamine -containing copolymers showed both good adhesion and solubility properties. Also, they exhibited better thermal stability than PVP homopolymer and such thermal properties were changed depending on the chemical composition and their $M_w$, which were evidenced by the measurement of oxygen induced temperature (OIT). From the OIT measurement, poly(4-vinyl pyridine- co-allylamine) was thermally stable up to $230^{\circ}C$ for 70 min in the 100% oxygen environment. As a result, allylamine-containing copolymers can be considered as a promising OSP coating material that has excellent thermal and adhesive properties applicable to the present microelectronic package processes.