• Journal of Korean Association for Spatial Structures
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• v.12 no.2
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• pp.45-53
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• 2012

This paper derives Isogeometric analysis and post-processing method of surface that are generated by NURBS basis function for accurate geometric modeling and structure analysis of free-form. By deforming these parameters that are consisted of control points, knots, polynomial, variable geometric models are derived. The basis function that is used to Isogeometric analysis is same to the basis function of NURBS that is used to generate geometric models. For performing isogeometric analysis, h-p-k refinement is performed without changing of original geometry. To visualize the results of isogeometric analysis that control points' displacements, post-processing method that is the interface method between IGES format and Rhinoceros is derived.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.3
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• pp.134-142
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• 2002

Quadtree, which is a hierarchical data structure, is a very important data structure to represent binary images. The linear quadtree representation as a way to store a quadtree is efficient to save space compared with other representations. Therefore, it has been widely studied to develop efficient algorithms to execute operations related with quadtrees. The window operation is one of important geometry operations in image processing, which extracts a sub-image indicated by a window in the image. In this paper, we present an algorithm to perform the window operation of binary images represented by quadtrees, using three-dimensional $n{\times}n{\times}n$ processors on RMESH(Reconfigurable MESH). This algorithm has constant-time complexity by using efficient basic operations to route the locational codes of quardtree on the hierarchical structure of $n{\times}n{\times}n$ RMESH.

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.141-149
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• 2008

In this research we present a novel method which combines and visualizes the design model and the FDM-based simulation result of solidification. Moreover we employ VR displays and visualize stereoscopic images to provide an effective analysis environment. First we reconstruct the solidification simulation result to a rectangular mesh model using a conventional simulation software. Then each point color of the reconstructed model represents a temperature value of its position. Next we map the two models by finding the nearest point of the reconstructed model for each point of the design model and then assign the point color of the design model as that of the reconstructed model. Before this mapping we apply mesh subdivision because the design model is composed of minimum number of points and that makes the point distribution of the design model not uniform compared with the reconstructed model. In this process the original shape is preserved in the manner that points are added to the mesh edge which length is longer than a predefined threshold value. The implemented system visualizes the solidification simulation data on the design model, which allows the user to understand the object geometry precisely. The immersive and realistic working environment constructed with use of VR display can support the user to discover the defect occurrence faster and more effectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.1
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• pp.672-679
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• 2018

This paper describes a methodology for shape design using an optimal design system, whereas generally a three dimensional analysis is required for such designs. An automatic finite element mesh generation technique, which is based on fuzzy knowledge processing and computational geometry techniques, is incorporated into the system, together with a commercial FE analysis code and a commercial solid modeler. Also, with the aid of multilayer neural networks, the present system allows us to automatically obtain a design window, in which a number of satisfactory design solutions exist in a multi-dimensional design parameter space. The developed optimal design system is successfully applied to evaluate the structures that are used. This study used a stress gauge to measure the maximum stress affecting the parts of the side housing bracket which are most vulnerable to cracking. Thereafter, we used a tool to interpret the maximum stress value, while maintaining the same stress as that exerted on the spot. Furthermore, a stress analysis was performed with the typical shape maintained intact, SM490 used for the material and the minimizing weight safety coefficient set to 3, while keeping the maximum stress the same as or smaller than the allowable stress. In this paper, a side housing bracket with a comparably simple structure for 36 tons was optimized, however if the method developed in this study were applied to side housing brackets of different classes (tons), their quality would be greatly improved.