• Journal of KIISE:Computing Practices and Letters
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• v.15 no.4
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• pp.270-274
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• 2009

In this paper, we propose an efficient computation method over GF($2^m$) for memory-constrained devices. While previous methods concentrated only on fast multiplication, we propose to reduce the amount of required memory by cleverly changing the order of suboperations. According to our experiments, the new method reduces the memory consumption by about 20% compared to the previous methods, and it achieves a comparable speed with them.

• Journal of the Korea Society of Computer and Information
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• v.21 no.1
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• pp.79-84
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• 2016

In this paper, we propose reliable message transmission scheme based on CoAP, considering the constrained feature of IoT device, such as low power, the limited memory size and low computing capacity. Recently, the various kinds of application protocol has been studied to support IoT environments. In particular, CoAP protocol was developed as application protocol for IoT at the IETF core WG. However, because CoAP protocol is deigned to be used in constrained node, this protocol uses UDP at transport layer. Thus, data loss may occur frequently in network congestion environments. The proposed scheme, in this paper, is to overcome the problem of frequent data loss with low overhead. Also it includes the function which is to minimize the data loss in sleep mode of IoT device.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.5
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• pp.975-981
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• 2017

In this paper, we propose a method for efficient use of energy when using flash device in WSN environment. Typical Flash devices have a drawback to be an energy efficient storage media in the energy-constrained WSNs due to the high standby energy. An energy efficient approach to deploy Flash devices into WSNs is simply turning the Flash device off whenever idle. In this regard, we make the simple but ideal approach realistic by removing these two obstacles by exploiting nonvolatile RAM (NVRAM), which is an emerging memory technology that provides both non-volatility and byte-addressability. Specifically, we make use of NVRAM as an extension of metadata storage to remove the FTL metadata scanning process that mainly incurs the two obstacles. Through the implementation and evaluation in a real system environment, we verify that significant energy savings without sacrificing I/O performance are feasible in WSNs by turning off the Flash device exploiting NVRAM whenever it becomes idle. Experimental results show that the proposed method consumes only about 1.087% energy compared to the conventional storage device.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.39-47
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• 2015

In this paper, we propose a new time synchronization algorithm using CoAP(constrained-application protocol) in sensor network environment, which handles a technique that synchronizes an explicit timestamp between sensor nodes not including an additional module for time-setting and sensor node gateway linked to internet time server. CoAP is a standard protocol for sensor data communication among sensor nodes and sensor node gateway to be built much less memory and power supply in constrained network surroundings including serious network jitter, packet losses, etc. We have supplied an exact time synchronization implementation among small and cheap IP-based sensor nodes or non-IP based sensor nodes and sensor node gateway in sensor network using CoAP message header's option extension. On behalf of conventional network time synchronization method, as our approach uses an exclusive protocol 'CoAP' in sensor network, it is not to become an additional burden for synchronization service to sensor nodes or sensor node gateway. This method has an average error about 2ms comparing to NTP service and offers a low-cost and robust network time synchronization algorithm.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.6
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• pp.369-375
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• 2017

In this paper, we present a self-adaptive software platform that enables an IoT gateway to perform autonomous operation considering IoT devices connected each other in resource-constrained environments. Based on the oneM2M device software platform publicly available, we have designed an additional part, called SAS (self-adaptive software) consisting of MAM (memory-aware module), NAM (network-aware module), BAM (battery-aware module), DAM (data-aware module), and DH (decision handler). A prototype system is implemented to show the feasibility of the proposed self-adaptive software architecture. Our proposed system demonstrates that it can adaptively adjust the operation of gateway and connected devices to their resource conditions under the desired service scenarios.

• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.135-136
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• 2018

CoAP을 사용하는 IoT 기기는 핸드오버를 시행하는 동안 주기적으로 보내야 하는 메시지를 보내지 않고 메모리에 저장한다. 그로 인한 경량 IoT 기기의 메모리 요구량의 감소를 위한 핸드오버 절차를 제안한다. 제안하는 절차에서는 센서 노드가 핸드오버 이전에 현재 기지국에 미리 핸드오버 요청을 보낸다. 따라서 센서 노드가 이웃한 기지국에게 핸드오버 요청을 했을 때, 이웃한 기지국은 현재 기지국에게 핸드오버 알림을 주지 않는다. 본 연구에서는 시뮬레이션을 통하여 제안하는 핸드오버 절차로 인한 observe 메시지의 메모리 점유율을 50%가량 줄인다.

• Journal of Information Processing Systems
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• v.15 no.6
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• pp.1406-1421
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• 2019

The Internet-of-Things (IoT) has been deployed in almost every facet of our day to day activities. This is made possible because sensing and data collection devices have been given computing and communication capabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet they are severely constrained in terms of memory capacitance, hardware area, and power consumption. With the increase in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handle control, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-cost devices is to examine the hardware resource utilization to make sure that it fulfills the requirements of the device. This paper gives an analysis of the hardware resource usage of ten synthesizable processors that implement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All the ten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports are extracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.

• Journal of Sensor Science and Technology
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• v.30 no.1
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• pp.20-24
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• 2021

The electrocardiogram (ECG) is one of the most extensively employed signals used to diagnose and predict cardiovascular diseases (CVDs). In recent years, several deep learning (DL) models have been proposed to improve detection accuracy. Among these, deep neural networks (DNNs) are the most popular, wherein the features are extracted automatically. Despite the increment in classification accuracy, DL models require exorbitant computational resources and power. This causes the mapping of DNNs to be slow; in addition, the mapping is challenging for a wearable device. Embedded systems have constrained power and memory resources. Therefore full-precision DNNs are not easily deployable on devices. To make the neural network faster and more power-efficient, spiking neural networks (SNNs) have been introduced for fewer operations and less complex hardware resources. However, the conventional SNN has low accuracy and high computational cost. Therefore, this paper proposes a new binarized SNN which modifies the synaptic weights of SNN constraining it to be binary (+1 and -1). In the simulation results, this paper compares the DL models and SNNs and evaluates which model is optimal for ECG classification. Although there is a slight compromise in accuracy, the latter proves to be energy-efficient.