• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.211-211
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• 2009

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.46-49
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• 1994

In this paper we investigate the characteristics of switching and memory traps in sealed MONOS nonvolatile memory devices with different nitride thicknesses. We have demonttrated flatband voltage shift of 1V with 5V programming voltage. By fitting the experimental observations with theoretical calculations, trap density and capture cross section of memory trap at the nitride-blocking oxide interface are estimated to be 1.0${\times}$10$\^$13/ cm$\^$-2/ and 8.0${\times}$10$\^$14/ cm$\^$-2/

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.261-261
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• 2016

플래시 메모리 (flash memory)는 DRAM(dynamic racdom access memory)이나 SRAM(static random access memory)에 비해 소자의 구조가 매우 단순하기 때문에 집적도가 높아서 기기의 소형화가 가능하다는 점과 제조비용이 낮다는 장점을 가지고 있다. 또한, 전원을 차단하면 정보가 사라지는 DRAM이나 SRAM과 달리 전원이 꺼지더라도 저장된 정보가 지워지지 않는다는 특징을 가지고 있어서 ROM(read only memory)과 정보의 입출력이 자유로운 RAM의 장점을 동시에 가지기 때문에 활용도가 크다. 또한, 속도가 빠르고 소비전력이 작아서 USB 드라이브, 디지털 TV, 디지털 캠코더, 디지털 카메라, 휴대전화, 개인용 휴대단말기, 게임기 및 MP3 플레이어 등에 널리 사용되고 있다. 특히, 낸드(NAND)형의 플래시 메모리는 고집적이 가능하며 하드디스크를 대체할 수 있어 고집적 음성이나 화상 등의 저장용으로 많이 쓰이며 일정량의 정보를 저장해두고 작업해야 하는 휴대형 기기에도 적합하며 가격도 노어(NOR)형에 비해 저렴하다는 장점을 가진다. 최근에는 smart watch, wearable device 등과 같은 차세대 디스플레이 소자에 대한 관심이 증가함에 따라 투명하고 유연한 메모리 소자에 대한 연구가 다양하게 진행되고 있으며 유리나 플라스틱과 같은 기판 위에서 투명한 플래시 메모리를 형성하는 기술에 대한 관심이 높아지고 있다. 전하트랩형 (charge trap type) 플래시 메모리는 플로팅 게이트형 플래시 메모리와는 다르게 정보를 절연막 층에 저장하므로 인접 셀간의 간섭이나 소자의 크기를 줄일 수 있기 때문에 투명하고 유연한 메모리 소자에 적용이 가능한 차세대 플래시 메모리로 기대되고 있다. 전하트랩형 플래시메모리는 정보를 저장하기 위하여 tunneling layer, trap layer, blocking layer의 3층으로 이루어진 게이트 절연막을 가진다. 전하트랩 플래시 메모리는 게이트 전압에 따라서 채널의 전자가 tunnel layer를 통해 trap layer에 주입되어 정보를 기억하게 되는데, trap layer에 주입된 전자가 다시 채널로 빠져나가는 charge loss 현상이 큰 문제점으로 지적된다. 따라서 tunnel layer의 막질향상을 위한 다양한 열처리 방법들이 제시되고 있으며, 기존의 CTA (conventional thermal annealing) 방식은 상대적으로 높은 온도와 긴 열처리 시간을 가지고, RTA (rapid thermal annealing) 방식은 매우 높은 열처리 온도를 필요로 하기 때문에 플라스틱, 유리와 같은 다양한 기판에 적용이 어렵다. 따라서 본 연구에서는 기존의 열처리 방식보다 에너지 전달 효율이 높고, 저온공정 및 열처리 시간을 단축시킬 수 있는 마이크로웨이브 열처리(microwave irradiation, MWI)를 도입하였다. Tunneling layer, trap layer, blocking layer를 가지는 MOS capacitor 구조의 전하트랩형 플래시 메모리를 제작하여 CTA, RTA, MWI 처리를 실시한 다음, 전기적 특성을 평가하였다. 그 결과, 마이크로웨이브 열처리를 실시한 메모리 소자는 CTA 처리한 소자와 거의 동등한 정도의 우수한 전기적인 특성을 나타내는 것을 확인하였다. 따라서, MWI를 이용하면 tunnel layer의 막질을 향상시킬 뿐만 아니라, thermal budget을 크게 줄일 수 있어 차세대 투명하고 유연한 메모리 소자 제작에 큰 기여를 할 것으로 예상한다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.167-173
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• 2017

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.59-63
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• 2015

This paper discusses the capacitance-voltage method in Metal-Oxide-Nitride-Oxide-Silicon (MONOS) devices to analyzed the characteristics of the top oxide/nitride, nitride/bottom oxide interface trap distribution. In the CV method, nitride trap density can be calculated based on the program characteristics of the nitride thickness variations. By applying this method, silicon rich nitride device found to have a larger trap density than stoichiometric nitride device. This result is consistent with previous studies. If this comparison analysis can be expected to result in improved reliability of the SONOS flash memory.

• Transactions on Electrical and Electronic Materials
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• v.16 no.3
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• pp.130-134
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• 2015

This research proposes the use of a composition modulated (ZrO₂)_x(Al₂O₃)_1-x film as a charge trapping layer for charge trap flash memory; this is possible when the Zr (Al) atomic percent is controlled to form a variable bandgap as identified by the valence band offsets and electron energy loss spectrum measurements. Compared to memory devices with uniform compositional (ZrO₂)_0.1(Al₂O₃)_0.9 or a (ZrO₂)_0.92(Al₂O₃)_0.08 trapping layer, the memory device using the composition modulated (ZrO₂)_x(Al₂O₃)_1-x as the charge trapping layer exhibits a larger memory window (6.0 V) at the gate sweeping voltage of ±8 V, improved data retention, and significantly faster program/erase speed. Improvements of the memory characteristics are attributed to the special energy band alignments resulting from non-uniform distribution of elemental composition. These results indicate that the composition modulated (ZrO₂)_x(Al₂O₃)_1-x film is a promising candidate for future nonvolatile memory device applications.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.1
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• pp.13-18
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• 1999

The trap density by the stress bias in silicon oxides with different thicknesses has been investigated. The trap density by stress bias was shown to be composed of on time current and off time current. The on time trap density was composed of dc current. The off time trap density was caused by the tunneling charging and discharging of the trap in the interfaces. The on time trap density was used to estimate to the limitations on oxide thicknesses. The off time trap density was used to estimate the data retention in nonvolatile memory devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.34-39
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• 2014

This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.449-457
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• 2012

The program/erase (P/E) cyclic endurances including bias temperature instability (BTI) behaviors of Metal-$Al_2O_3$-Nitride-Oxide-Semiconductor (MANOS) memories are investigated in comparison with those of Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) memories. In terms of BTI behaviors, the SONOS power-law exponent n is ~0.3 independent of the P/E cycle and the temperature in the case of programmed cell, and 0.36~0.66 sensitive to the temperature in case of erased cell. Physical mechanisms are observed with thermally activated $h^*$ diffusion-induced Si/$SiO_2$ interface trap ($N_{IT}$) curing and Poole-Frenkel emission of holes trapped in border trap in the bottom oxide ($N_{OT}$). In terms of the BTI behavior in MANOS memory cells, the power-law exponent is n=0.4~0.9 in the programmed cell and n=0.65~1.2 in the erased cell, which means that the power law is strong function of the number of P/E cycles, not of the temperature. Related mechanism is can be explained by the competition between the cycle-induced degradation of P/E efficiency and the temperature-controlled $h^*$ diffusion followed by $N_{IT}$ passivation.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.