• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.8-15
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• 1993

A concrete disign of memory circuit is presented aiming at the application of sliding diagonal test patterns. A modification of sliding diagonal test pattern includes the complexity reduction from O(n$^{32}$) to O(n) using parallel test memory concept. The control circuit design was based on delay-element, and verified via logic and circuit simulation. Area overhead was evaluated based on physical layout using a 0.7 micron design rule resulting in about 1% area increase for a typical 16Mbit DRAM.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.69-72
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• 2007

No doubt that more vast data and precise values are required for the detailed and accurate analysis result. People's expectation for the output of space application goes higher, and consequently satellite memory system has to process massive data faster. This paper reviews memory systems of KOMPSAT (Korea Multi-Purpose SATellite) series and try to find a suitable memory system structure to process data more faster not at device level but at system level.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.105-113
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• 2004

This paper presents a design method for an asynchronous memory with a completion signal generation circuit meeting D-I model. The proposed design method is to generates a completion signal with dummy cell and a completion signal generation circuit to indicate completion of the required read or write operation to the processor. Dividing a memory exponentially to consider delay of a bit-line and a memory cell makes memory operates as a D-I model with minimum addition of redundant circuit. The proposed memory partitioning algorithm that divides entire memory into the several partitions with a exponentially increased size reduces the memory access delay by 40% compared with a conventional partitioning method to the same size.

• Proceedings of the KIEE Conference
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• 2004.05a
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• pp.153-155
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• 2004

In this paper, we design the memory tester chip playing an important role in the memory tester as central parts. Memory tester has the sixteen inner instructions to control the test sequence and the address and data signals to DUT. These instructions are saved in memory with each block such as sequencer and pattern generator. Sequencer controls the test sequence according to instructions saved in the memory. And Pattern generator generates the address and data signals according to instructions saved in the memory, too. We can use these chips for various functional test of memory.

• Journal of Korea Multimedia Society
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• v.24 no.7
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• pp.922-932
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• 2021

This thesis mainly studies the impact of short-term memory in VR tour games on users. The thesis is based on VR tour games and short-term memory, using the literature research method, the practical research method, and the investigation method. First, the author designs and makes VR tour games on the Beijing-Hangzhou Grand Canal, and then conducts a questionnaire survey and designs a control experiment. The experiment explores the differences of the short-term memory level of individuals between the normal environment and the VR tour game environment. It verifies whether the influential hypothesis proposed by the research is correct. Research conclusions show that: VR tour games have an impact on short-term memory. Compared with the normal environment, the subjects have better performance in the VR tour game mode and can maintain a high short-term memory level for a longer time. Its conclusions should promote the cultural propaganda of scenic spots and provide theoretical support for tourists' short-term memory of scenic spots culture.

• Journal of Korea Multimedia Society
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• v.23 no.2
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• pp.293-300
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• 2020

Since the communication networks like the Internet collapses at disaster and calamity sites, a maintenance system that can be operated offline is required for the maintenance of various facilities. In this paper, we propose a system that memory tags attached on the facilities may transmit the emergency manual to a smart-phone, and the smart phone displays it off-line. The main issue is to design low energy mode memory tags. This study presents two kinds of methods and analyzes each's energy consumption mode. The first one is to develop memory tags by using one chip, and the next one is to design memory tags by forming multi-modules. Both ways show proper application fields under the low energy mode. This research selects the off-line maintenance system by using one chip design, and proposes the direction of contents for enhancing the effectiveness of the system. And we expect that this memory tags will be valuable for disaster scenes as well as battle fields.

• Journal of Sensor Science and Technology
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• v.7 no.6
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• pp.437-445
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• 1998

The actuator using shape memory alloy spring with bias spring can act as a bidirectional actuator due to the restoring force of the bias spring. In the design of shape memory actuator with bias spring, the required design specifications are the generated force and the necessary stroke. To fulfill these requirements, shape memory alloy spring and bias spring should be designed carefully considering the specified application. In this paper, the novel design method for shape memory alloy actuator with bias spring, which does not require any assumptions from experience, has been proposed and verified by the test of fabricated shape memory alloy actuator. The experimental results show good agreements with calculated values, which guarantees the practical validity of our proposed design method.

• The Journal of the Korea Contents Association
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• v.8 no.9
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• pp.27-33
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• 2008

This paper designs Shared Memory on the Dual Core system so that it operates a general System V IPC on the Linux O.S. Shared Memory is the technique that many processes can access to identical memory area. We treat Shared Memory which is SVR in a kernel step. We design a share memory facility of Linux operating system on the Dual Core System. In this paper the suggesting of share memory facility design plan in Dual Core system is enhance the performance in existing an unity processor system as a dual core practical use. We attemp a performance enhance in each CPU for each process which uses a share memory.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.3
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• pp.151-156
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• 2015

Recently, an embedded flash memory has been widely used for the Internet of Things(IoT). Due to its nonvolatility, economical feasibility, stability, low power usage, and fast speed. With respect to power consumption, the embedded memory system must consider the most significant design factor. The objective of this research is to design high performance and low power NAND flash memory architecture including a dual buffer as a replacement for NOR flash. Simulation shows that the proposed NAND flash system can achieve better performance than a conventional NOR flash memory. Furthermore, the average memory access time of the proposed system is better that of other buffer systems with three times more space. The use of a small buffer results in a significant reduction in power consumption.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.924-927
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• 2003

In this paper, we design the memory tester chip set playing an important role in the memory tester as central parts. Memory tester has the sixteen inner instructions to control the test sequence and the address and data signals to DUT. These instructions are saved in memory with each chip such as sequence chip and address/data generator chip. Sequence chip controls the test sequence according to instructions saved in the memory. And Generator chip generates the address and data signals according to instructions saved in the memory, too.