• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.43.5-43
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• 2001

This paper considers a new synthesis of the optimally performing brain-state-in-a-box (BSB) neural associative memory given a set of prototype patterns to be stored as asymptotically stable equilibrium points with the large and uniform size of the domain of attraction (DOA). First, we propose a new theorem that will be used to provide a guideline in design of the BSB neural associative memory. Finally, a design example is given to illustrate the proposed approach and to compare with existing synthesis methods.

• Journal of Internet Computing and Services
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• v.6 no.4
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• pp.47-58
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• 2005

There are two major type of flash memory products, namely, NAND-type and NOR-type flash memory. NOR-type flash memory is generally deployed as ROM BIOS code storage because if offers Byte I/O and fast read operation. However, NOR-type flash memory is more expensive than NAND-type flash memory in terms of the cost per byte ratio, and hence NAND type flash memory is more widely used as large data storage such as embedded Linux file systems. In this paper, we designed an efficient flash memory file system based an Embedded system and presented to make up for reduced to Swapping a weak System Performance to flash file system using NAND-type flash memory, then proposed Swapping algorithm insured to an Execution time. Based on Implementation and simulation studies, Then, We improved performance bases on NAND-type flash memory to the requirement of the embedded system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.436-439
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• 2011

As mobile digital devices have come into more widespread use, the demand for mobile storage devices have been increasing rapidly and most of digital cameras and camcorders are using SD memory cards. The SD memory card are generally employing a form of copying data into a personal computer after storing user data based on flash memory. The current paper proposes the SD memory card of being capable of storing photograph and image data through network rather than using a method of storing data in flash memory. By delivering data and memory address values obtained through SD Slave IP to network server without sending them to flash memory, one can store data necessary to be stored in a computer's SD memory in real time in a safe and convenient way.

• Journal of Korean Academy of Nursing
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• v.47 no.3
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• pp.431-444
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• 2017

Purpose: This study was conducted to verify the effects of a memory and visual-motor integration program for older adults based on self-efficacy theory. Methods: A non-equivalent control group pretest-posttest design was implemented in this quasi-experimental study. The participants were 62 older adults from senior centers and older adult welfare facilities in D and G city (Experimental group=30, Control group=32). The experimental group took part in a 12-session memory and visual-motor integration program over 6 weeks. Data regarding memory self-efficacy, memory, visual-motor integration, and depression were collected from July to October of 2014 and analyzed with independent t-test and Mann-Whitney U test using PASW Statistics (SPSS) 18.0 to determine the effects of the interventions. Results: Memory self-efficacy (t=2.20, p=.031), memory (Z=-2.92, p=.004), and visual-motor integration (Z=-2.49, p=.013) increased significantly in the experimental group as compared to the control group. However, depression (Z=-0.90, p=.367) did not decrease significantly. Conclusion: This program is effective for increasing memory, visual-motor integration, and memory self-efficacy in older adults. Therefore, it can be used to improve cognition and prevent dementia in older adults.

• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.1
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• pp.14-17
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• 2005

In this paper, an automated methodology for generating model parameters considering real manufacturing processes is presented with verified results. In addition, the outcomes of applications to the next generation of flash memory devices using the parameters calibrated from the process specification decision are analyzed. The test vehicle is replaced with a well-calibrated TCAD simulation. First, the calibration methodology is introduced and tested for a flash memory device. The calibration errors are less than 5% of a full chip operation, which is acceptable to designers. The results of the calibration are then used to predict the I-V curves and the model parameters of various transistors for the design of flash devices.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09a
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• pp.256-257
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• 2006

3D printing of NiTi alloys has been successfully achieved. A novel printing process has been developed and used, which consists in selective deposition of a solvent on a granule bed. The granules are composed of metal powders and thermoplastic binder, which are mixed and sieved by conventional methods. A sound green strength is obtained after solvent evaporation. Sintered parts exhibit good density, proper phase composition and shape memory behaviour.

• Korean Medical Education Review
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• v.12 no.2
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• pp.27-33
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• 2010

The purpose of this study was to review the definition of cognitive load (CL), the relationship between CL and instructional design, and to provide a viewpoint of CL in curriculum and instructional design in medical education. Cognitive load theory (CLT) makes use of three hypotheses about the structure of human memory: working memory (WM) is limited in terms of the amount of information it can hold, in contrast with WM, long term memory is assumed to have no limits and organizes information as schemata. CL indicates the mental load on the limitation of WM. CLT has been used to design instructional interventions that help to ease the learning process. Extraneous CL is related to irrelevant instructional interventions, while intrinsic CL is the complexity of the information itself. Germane CL is the cognitive process for acquiring schema formation. It is a necessary CL to achieve deeper comprehension and solve problems. The range of medical education includes complex, multifaceted and knowledge-rich domains with clinical skills and attitudes. Therefore, CLT may be used to guide instructional design in medical education in terms of decreasing extraneous CL, adjusting intrinsic CL and enhancing the germane CL.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1081-1090
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• 2013

In this paper, a C-band 10 W power amplifier with internally matched input and output matching circuit is designed and fabricated. The used power transistor for the power amplifier is GaAs pHEMT bare-chip. The wire bonding analysis considering the size of the capacitor and the position of transistor pad improves the accurate design. The matching circuit design with the package effect using EM simulation is performed. To reduce the unsymmetry of IMD3 in 2-tone measurement due to the memory effect, the bias circuit minimizing the memory effect is proposed and employed. The measured $P_{1dB}$, power gain, and power added efficiency are 39.8~40.4 dBm, 9.7~10.4 dB, and 33.4~38.0 %, respectively. Adopting the proposed bias circuit, the difference between the upper and lower IMD3 is less than 0.76 dB.

• Journal of the Korea Society of Computer and Information
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• v.25 no.10
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• pp.125-133
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• 2020

In this paper, we design 4-layer TCP/IP that utilizes minimal memory and processor resources in Internet of Things(IoT) systems. The TCP/IP designed in this paper has the following characteristics. First, memory resource is minimized by using minimal memory allocation. Second, processor resource is minimized by using minimal memory copy. Third, the execution time of the TCP/IP can be completed in a deterministic time. Fourth, there is no memory leak problem. The standard in minimal resources for memory and processor derived in this paper can be used to check whether the network subsystems of the already implemented IoT systems are efficiently implemented. As the result of measuring the amount of memory allocation and copy of the network subsystem of Zephyr, an open source IoT kernel recently released by the Linux Foundation, we found that it was bigger than the standard in minimal resources derived in this paper. The network subsystem of Zephyr was improved according to the design proposed in this paper, confirming that the amount of memory allocation and copy were decreased by about 39% and 67%, respectively, and the execution time was also reduced by about 28%.

• Journal of Satellite, Information and Communications
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• v.12 no.4
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• pp.115-119
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• 2017

Intermodulation distortion degrades the S/N(signal-to-noise) of the original signal and also affects the adjacent channels. Intermodulation distortion is mainly caused by the nonlinear characteristics of the power amplifier. If the power amplifier with nonlinear characteristics has a memory effect, the intermodulation distortions occurred in the power amplifier are generated in various and complex forms. The predistorter is used as a way to improve intermodulation distortions. In order to efficiently utilize the performance of the predistorter, the memory effect of the power amplifier must be reduced. In this paper, we describe the design method of bias circuit to reduce the memory effect in power amplifiers. To reduce the memory effect, the bias circuit must have a high impedance for the signal and a low impedance for the envelope(modulating signal) and the second harmonic component of the signal. To verify the performance of the bias circuit designed considering the memory effect, a power amplifier operating at 170 ~ 220MHz was designed and implemented. The designed bias circuit has a large impedance in the operating frequency band and low impedance in the envelope signal and the second harmonic of the signal. As a result of the performance measurement, it was found that the asymmetric intermodulation distortion component is improved by 3.7dB.