• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.191-193
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• 2005

Flash memories are one of best media to support portable computer's storages. However, we need to improve traditional data management scheme due to the relatively slow characteristics of flash operation as compared to RAM memory. In order to achieve this goal, we devise a new scheme called Flash Two Phase Locking (F2PL) scheme for efficient data processing. F2PL improves transaction performance by allowing multi version reads and efficiently handling slow flash write/erase operation in lock management process.

• ETRI Journal
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• v.31 no.3
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• pp.339-341
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• 2009

Built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. In this letter, a new BIRA method for both high repair efficiency and small hardware overhead is presented. The proposed method performs redundancy analysis operations using the spare mapping registers with a covered fault list. Experimental results demonstrate the superiority of the proposed method compared to previous works.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.927-936
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• 1988

This paper proposes a pipelined memory access method as a new technique for a bus interface between processors and memories in tightly coupled multiprocessor systems. Since the shared bus is bottle neck of the system, model of pipelined access to memory has been developed. Results of the evaluation by the discrete time Markov model showed a significant improvement of the efficiency.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.178-186
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• 1996

This paper proposes a new design technique that can be used for BSB (brain-state-in-a-box) neural networks to realize autoassociative memories. The proposed method is based on the parametrization of solution space and optimization using genetic algorithm. The applicability of the established technique is demonstrated by means of a simulation example, which illustrates its strengths.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.240-242
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• 2009

Flash memories are one of best media to support future computer's storages. However, we need to improve traditional data management scheme due to the relatively slow characteristics of flash operation of SSD. Due to the unique characteristics of flash media and hard disk, the efficiency of I/O processing is severely reduced without special treatment, especially in the presence of heavy workload or bulk data copy. In this respect, we need to design and develop efficient hybrid-RAID storage system.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.43.5-43
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• 2001

This paper considers a new synthesis of the optimally performing brain-state-in-a-box (BSB) neural associative memory given a set of prototype patterns to be stored as asymptotically stable equilibrium points with the large and uniform size of the domain of attraction (DOA). First, we propose a new theorem that will be used to provide a guideline in design of the BSB neural associative memory. Finally, a design example is given to illustrate the proposed approach and to compare with existing synthesis methods.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.115.3-115
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• 2001

In this paper, discrete-time cellular neural networks are designed in order to function as associative memories by using Hebbian learning rule and non-cloning template. The proposed method has a very simple structure to design and to learn. Weights are updated by the connection between the neuron and its neighborhood. In the simulation, the proposed method is applied to the classification of a traffic sign pattern.

• 제어로봇시스템학회:학술대회논문집
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• 1999.10a
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• pp.210-213
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• 1999

Anyone observes that information processing in animal brains is depended on neural networks. On the other hand, engineering models for the neural networks are well known now, and they have been studied, and learning facility is found in the model. We are sure there is a potential in order to create a non Neuman-machine in the engineering models. We studied iteration forms including the engineering neural network models, taking a first step for the creation.

• Communications for Statistical Applications and Methods
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• v.16 no.4
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• pp.639-645
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• 2009

Fractional Brwonian motion(fBm) has properties of behaving tails and exhibiting long memory while remaining Gaussian. In particular, it is well known that interest rates show some long memories and non-Markovian. We present no aribitrage condition for HJM model under the multi-factor fBm reflecting the long range dependence in the interest rate model.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.29-29
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• 2000

This paper describes the design and implementation of a high-speed navigation computer to achieve precision navigation performance with Strapdown INS. The navigation computer inputs are velocity and angular increment data from the ISA at the signal of the 2404Hz interrupt and performs the removal of gyro block motion and the compensation of high dynamic errors at the 200Hz. For high-speed and high-accuracy, the computer consists of the 68040 micro-processor, 128k Memories, FPGAs, and so on. We show that the computer satisfies the required performance by In-Run navigation tests.