• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.865-870
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• 2003

A motion controller has been used variously in industry such as semiconductor manufacture equipment, industrial robot, assembly/conveyor line applications and CNC equipment. There are several types of controller in motion control. One of these is a PC-based motion controller such as PCI or ISA, and another is stand-alone motion controller. The PC bus-based motion controller is popular because of improving bus architectures and GUI (Graphic User Interface) that offer convenience of use to user. There are some problems in this. The PC bus-based solution allows for only one of the form factors, so it has a poor flexibility. The overall system package size is bigger than other motion control system. And also, additional axes of control require additional slot, however the number of slots is limited. Furthermore, unwieldy and many wirings come to connect plants or I/O. The stand-alone motion controller has also this limit of axes of control and wiring problems. To resolve these problems, controller must have capability of operating as stand-alone devices that resides outside the computer and it needs network capability to communicate to each motion device. In this paper, a network-based stand-alone motion system is proposed. This system integrates PC and motion controller into one stand-alone motion system, and uses CAN (Controller Area Network) as network protocol. Single board computer that is type of 3.5" FDD form factor is used to reduce the system size and cost. It works with Windows XP Embedded as operating system. This motion system operates by itself or serves as master motion controller that communicates to slave motion controller. The Slave motion controllers can easily connect to master motion system through CAN-network.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.54-60
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• 2008

The bus architecture consists of a master initiating a communication transaction, a slave responding to the transaction, a arbiter selecting a master, a bridge connecting buses and so on. Recently this is more complicated and developed toward multi-bus architecture. In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory selector is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.175-182
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• 2011

In this paper, we implemented a high-performence memory controller which can accommodate processing blocks(multiple masters) in SoC for video signal processing. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Selector, Mster Arbiter, Memory Signal Generator, Command Decoder, and memory Signal Generator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used. Since the designed H/W can be stably operated in 174.28MHz, it satisfies the specification of SDRAM technology.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.11
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• pp.1099-1105
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• 2007

In this paper, modified two-port time-domain passivity approach is proposed for stable bilateral control of teleoperators under time-varying communication delay. We separate input and output energy at each port of a bilateral controller, and propose a sufficient condition for satisfying the passivity of the bilateral controller including time-delay. Output energy at the master port should be less than the transmitted input energy from the slave port with time-delay, and output energy at the slave port should be less than the transmitted input energy from the master port with time-delay. For satisfying above two conditions, two passivity controllers are attached at each port of the bilateral controller. A packet reflector with wireless internet connection is used to introduce serious time-varying communication delay of teleoperators. Average amount of time-delay was about 190(msec) for round trip, and varying between 175(msec) and 275(msec). Moreover some data packet was lost during the communication due to UDP data communication. Even under the serious time-varying delay and packet loss communication condition, the proposed approach can achieve stable teleoperation in free motion and hard contact as well.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.9
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• pp.1540-1548
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• 2010

KEPCO proposes enhanced voltage management system that is a coordinate voltage control system between the hierarchical voltage control system and the slow voltage control system. It has been installing in Jeju island. VMS consists of a master controller, CVC (Continuous Voltage Controller) and DVC (Discrete Voltage Controller). CVC consists of main controller, FDMU (Field Data Measurement Unit) and several RPDs (Reactive Power Dispatcher). CVC has a control scheme with AVRs of generator to maintain the voltage of a pilot bus in a power system, DVC has a control scheme with static reactive power sources, like a shunt capacitor, a shunt reactor, ULTC and so on, to maintain the reactive power reserve of a power system and a master controller is executed to recover reactive power margin of a power system through coordinated control between CVC and DVC.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.173-173
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• 2000

This paper discusses a observer based discrete-time controller design and presents a modified control structure for dual-stage hard disk drive systems using piezoelectric microactuator(MA). In plant modeling, dynamic coupling between VCM and MA is not considered. Each controller is organized independently and designed using pole placement. Simulation result shows that 4th-order controller achieves about 3kHz servo bandwidth and 0.22msec of 2% settling time.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.53 no.2
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• pp.94-99
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• 2004

In this paper, We design a RF control system capable of handling multiple POS thermal printers. The system has three parts including embedded master controller, RF controller and high-speed thermal printer. Specially the designed linux embedded controller has simple structure and high performance to connect the TCP/IP network. The effectiveness of the developed RF control system is shown by proposed food ordering system.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.1
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• pp.33-38
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• 2007

In this paper, hardware implementation of interface and control between two robots, the master and the slave robot, are designed. The master robot is the motion capturing device that captures motions of the human operator who wears it. The slave robot is the corresponding humanoid robot arms. Captured motions from the master robot are transferred to the slave robot to follow after the master. All hardware designs such as PID controllers, communications between the master robot, encoder counters, and PWM generators are embedded on a single FPGA chip. Experimental studies are conducted to demonstrate the performance of the FPGA controller design.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.10b
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• pp.1529-1532
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• 2001

ACE 2000 ATM 교환기를 이용하여 MPLS 교환기를 구현 시, ATM 가입자 및 중계선을 수용하여 스위치와 정합 기능을 수행하는 AIM(ATM interface module)에 IP 패킷에 대한 룩업을 수행하여 ATM 스위치로 패킷을 포워딩하는 HFEA(High performance Forwarding Engine board Assembly)를 연동하기 위해서는 UTOPIA Level2 연결이 요구된다. 그러나 HFEA 에서 622Mbps 급 성능의 MXT4400(SAR) 칩은 TSAR(Transmit SAR)로 운용 시 Master모드로 동작하게 되고, AIM 모듈 또한 Rx에서 Master모드로 동작하기 때문에 이들을 연결하기 위해서는 양 모듈간에서 Slave 모드로 동작할 수 있는 UTOPIA Controller가 필요하게 된다. 이에 따라 ALMA(AW Layer Module Assembly)칩과 HFEA TSAR 사이에서 데이터를 전달하는 UTOPIA Controller를 Xilinx를 이용해 FPGA로 구현하였다.

• Journal of Biomedical Engineering Research
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• v.29 no.1
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• pp.32-39
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• 2008

This paper reports on a realtime OS based master-slave configuration robot control system for laparoscopic surgery robot which enables telesurgery and overcomes shortcomings with conventional laparoscopic surgery. Surgery robot system requires control system that can process large volume information such as medical image data and video signal from endoscope in real-time manner, as well as precisely control the robot with high reliability. To meet the complex requirements, the use of high-level real-time OS (Operating System) in surgery robot controller is a must, which is as common as in many of modem robot controllers that adopt real-time OS as a base system software on which specific functional modules are implemened for more reliable and stable system. The control system consists of joint controllers, host controllers, and user interface units. The robot features a compact slave robot with 5 DOF (Degree-Of-Freedom) expanding the workspace of each tool and increasing the number of tools operating simultaneously. Each master, slave and Gill (Graphical User Interface) host runs a dedicated RTOS (Real-time OS), RTLinux-Pro (FSMLabs Inc., U.S.A.) on which functional modules such as motion control, communication, video signal integration and etc, are implemented, and all the hosts are in a gigabit Ethernet network for inter-host communication. Each master and slave controller set has a dedicated CAN (Controller Area Network) channel for control and monitoring signal communication with the joint controllers. Total 4 pairs of the master/slave manipulators as current are controlled by one host controller. The system showed satisfactory performance in both position control precision and master-slave motion synchronization in both bench test and animal experiment, and is now under further development for better safety and control fidelity for clinically applicable prototype.