• 전자공학회논문지C
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• 제34C권5호
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• pp.1-17
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• 1997

With the increasing performance and density of VLSI scircuits as well as the popularity of portable devices such as personal digital assitance, power consumption has emerged as an important issue in the design of electronic systems. Low power design techniqeus have been pursued at all design levels. However, it is more effective to attempt to reduce power dissipation at higher levels of abstraction which allow wider view. In this paper, we propose a simultaneous scheduling and binding scheme which increases the correlation between cosecutive inputs to an operation so that the switched capacitance of execution units is reduced in datapath-dominated circuits. The proposed method is implemented and integrated into the scheduling and assignment part of HYPER synthesis environment. Compared with original HYPER synthesis system, average power saving of 23.0% in execution units and 14.2% in the whole circuits, ar eobtained for a set of benchmark examples.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권1호
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• pp.19-29
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• 2002

A simple and analytical design approach for input power matched CMOS RF LNA circuits and their scaling for lower power consumption, is introduced. In spite of the simplicity of our expressions, it gives excellent agreement with numerical simulation results using commercial CAD tools for several circuit examples performed at 2.4GHz using $0.18\mu\textrm{m}$ CMOS technology. These simple and analytical results are extremely useful in that they can provide enough insights not only for designing any CMOS LNA circuits, but also for characterizing and diagnosing them whether being prototyped or manufactured.

• ETRI Journal
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• 제28권6호
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• pp.732-738
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• 2006

In this paper, novel CMOS pseudo-exponential circuits operating in a class-AB mode are presented. The pseudo-exponential approximation employed is based on second order equations. Such terms are derived in a straightforward way from the inherent nonlinear currents of class-AB transconductors. The cells are appropriate to be integrated in portable equipment due to their compactness and very low power consumption. Measurement results from a fabricated prototype in a 0.5 ${\mu}m$ technology reveal a range of 45 dB with errors lower than ${\pm}0.5$ dB, a power consumption of 100 ${\mu}W$, and an area of 0.01 $mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.436-442
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• 2014

A new bus-invert coding circuit, called Two-bit Bus-Invert Coding (TBIC) is presented. TBIC partitions a bus into a set of two-bit sub-buses, and applies the bus-invert (BI) algorithm to each sub-bus. Unlike ordinary BI circuits using invert-lines, TBIC does not use an invert-line, so that it sends coding information through a bus-line. To transmit 3-bit information with 2 bus-lines, TBIC allows one bus-line to have a mid-level state, called M-state. TBIC increases the performance of BI algorithm, by suppressing the generation of overhead transitions. TBIC reduces bus transitions by about 45.7%, which is 83% greater than the maximum achievable performance of ordinary BI with invert-lines.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권3호
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• pp.166-176
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• 2007

Radio frequency (RF) microelectromechanical systems (MEMS) have been pursued for more than a decade as a solution of high-performance on-chip fixed, tunable and reconfigurable circuits. This paper reviews our research work on RF MEMS switches and switching circuits in the past five years. The research work first concentrates on the development of lateral DC-contact switches and capacitive shunt switches. Low insertion loss, high isolation and wide frequency band have been achieved for the two types of switches; then the switches have been integrated with transmission lines to achieve different switching circuits, such as single-pole-multi-throw (SPMT) switching circuits, tunable band-pass filter, tunable band-stop filter and reconfigurable filter circuits. Substrate transfer process and surface planarization process are used to fabricate the above mentioned devices and circuits. The advantages of these two fabrication processes provide great flexibility in developing different types of RF MEMS switches and circuits. The ultimate target is to produce more powerful and sophisticated wireless appliances operating in handsets, base stations, and satellites with low power consumption and cost.

• 센서학회지
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• 제26권4호
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• pp.292-296
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• 2017

It has become ever harder to design reliable circuits with each nanometer technology node under normal operation conditions, a transistor device can be affected by various aging effects resulting in performance degradation and eventually design failure. The reliability (aging) effect has traditionally been the area of process engineers. However, in the future, even the smallest of variations can slow down a transistor's switching speed, and an aging device may not perform adequately at a very low voltage. Because of such dilemmas, the transistor aging is emerging as a circuit designer's problem. Therefore, in this paper, the impact of aging effects on the delay and power dissipation of digital circuits by using nanomneter MOSFET power gating structure has been analyzed.. Based on this analyzed aging models, a reliable digital circuits can be designed.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 추계학술대회
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• pp.527-530
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• 2016

본 논문에서는 $0.35-{\mu}m$ standard CMOS 공정에서 낮은 전력을 소모하면서 낮은 전원전압에서 동작하는 곡률보상 기능을 갖는 기준전류/전압 발생 회로를 제안한다. 제안된 회로는 weak-inversion 영역에서 동작하는 MOS 트랜지스터들을 사용함으로써 1V 이하 전원전압에서 동작할 수 있다. 시뮬레이션 결과는 제안되는 곡률보상 기술을 사용하여 기존의 곡률보상 기능이 없는 BGR 회로들처럼 종 모양이 아닌 사인 곡선과 같은 모양을 나타내 작은 TC 값을 보여준다. 제안된 회로들은 모두 0.9V의 전원전압에서 동작한다. 먼저, 기준전압 발생 회로는 176nW 전력을 소모하며, 온도 계수는 $26.4ppm/^{\circ}C$이다. 기준전류 발생 회로는 194.3nW 전력을 소모하며, 온도 계수는 $13.3ppm/^{\circ}C$이다.

• Transactions on Electrical and Electronic Materials
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• 제17권6호
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• pp.317-328
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• 2016

Over the past few decades, CMOS current comparators have been used in a wide range of applications, including analogue circuits, MVL (multiple-valued logic) circuits, and various electronic products. A current comparator is generally used in an ADC (analog-to-digital) converter of sensors and similar devices, and several techniques and approaches have been implemented to design the current comparator to improve performance. To this end, this paper presents a bibliographical survey of recently-published research on different current comparator topologies for low-power and high-speed applications. Moreover, several aspects of the CMOS current comparator are discussed regarding the design implementation, parameters, and performance comparison in terms of the power dissipation and operational speed. This review will serve as a comparative study and reference for researchers working on CMOS current comparators in low-power and high-speed applications.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권7호
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• pp.458-461
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• 2005

Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. This paper shows freezing of combinational logic parts during scan shift operation in test mode. The freezing technique leads to power to minimization. Significant power reduction in the scan techniques is achieved on ISCAS 89 benchmarks.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.79-82
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• 2003

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to $V_{ref}-V_{TH}$, where $V_{ref}=V_{DD}-nV_{TH}$. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we propose a low-power $4\times4$ bit parallel multiplier. The proposed circuits are simulated with HSPICE under $0.35{\mu}m$ CMOS standard technology. Compare to the previous works, this circuit can reduce the power consumption rate of 11.2% and the power-delay product of 10.3%.