• Journal of Institute of Control, Robotics and Systems
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• v.20 no.7
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• pp.767-773
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• 2014

The carrier-to-noise power ratio is a key parameter for determining the reliability of PVT (Position, Velocity, and Time) solutions which are obtained by a GNSS (Global Navigation Satellite System) receiver. It is also used for locking a tracking loop, deciding the re-acquisition process, and processing advanced navigation in the receiver subsystem. The representative carrier-to-noise power ratio estimation schemes are the narrowband-wideband power ratio method (NW), the MM (Moment Method), and Beaulieu's method (BL). The NW scheme is the most classical one for commercial GNSS receivers. It is often used as an authoritative benchmark for assessing carrier-to-noise power estimation schemes. The MM scheme is the least biased solution among them, and the BL scheme is a simpler scheme than the MM scheme. This paper focuses on the less biased estimation with low complexity when the residual phase noise remains, then proposes a novel carrier-to-noise power ratio estimation scheme with low complexity for GNSS receivers. The asymptotic bias of the proposed scheme is derived and compared with others, and the simulation results demonstrate that the complexity of the proposed scheme is lowest among them, while the estimation performance of the proposed scheme is similar to those of the BL and MM schemes in normal and high gained reception environments.

• Journal of electromagnetic engineering and science
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• v.4 no.4
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• pp.143-149
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• 2004

This paper describes characteristics of the single-balanced low IF resistive FET mixer for the digital beam forming(DBF) receiver. This DBF receiver based on the direct conversion method is designed with Low IF I and Q channel. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(IF) considered in this research are 1950 MHz, 1940 MHz and 10 MHz, respectively. Super low noise HJ FET of NE3210S01 is considered in design. The measured results of the proposed mixer are observed IF output power of -22.8 dBm without spurious signal at 10 MHz, conversion loss of -12.8 dB, isolation characteristics of -20 dB below, 1 dB gain compression point(PldB) of -3.9 dBm, input third order intercept point(IIP3) of 20 dBm, output third order intercept point(OIP3) of 4 dBm and dynamic range of 30 dBm. The proposed mixer has 1.0 dB higher IIP3 than previously published single-balanced resistive and GaAs FET mixers, and has 3.0 dB higher IIP3 and 4.3 dB higher PldB than CMOS mixers. This mixer was fabricated on 0.7874 mm thick microstrip $substrate(\varepsilon_r=2.5)$ and the total size is $123.1\;mm\times107.6\;mm$.

• Journal of electromagnetic engineering and science
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• v.2 no.2
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• pp.117-123
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• 2002

This paper describes the design for the resistive FET mixer with low If for the 4-Ch DBF(Digital Beam Forming) receiver This DBF receiver based on the direct conversion method is generally suitable for high-speed wireless mobile communications. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(If) considered in this research are 2.09 GHz, 2.08 CHz and 10 MHz, respectively. This mixer is composed of band pass filter, a low pass filter and a DC bias circuit. Super low noise HJ FET of NE3210S01 is considered in design. The RE input power, LO input power and Vcs are used -10 dBm, 6 dBm and -0.4 V, respectively. In the 4-Ch resistive FET mixer, the measured If and harmonic components of 10 MHe, 20 MHz and 2.087 CHz are about -19.2 dBm, -66 dBm and -48 dBm, respectively The If output power observed at each channel of 10 MHz is about -19.2 dBm and it is higher 28.8 dBm than the maximum harmonic component of 2.087 CHz. Each If output spectrum of the 4-Ch is observed almost same value and it shows a good agreement with the prediction.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.426-432
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• 2012

A fully-integrated low power K-band radar transceiver in 130 nm CMOS process is presented. It consists of a low-noise amplifier (LNA), a down-conversion mixer, a power amplifier (PA), and a frequency synthesizer with injection locked buffer for driving mixer and PA. The receiver front-end provides a conversion gain of 19 dB. The LNA achieves a power gain of 15 dB and noise figure of 5.4 dB, and the PA has an output power of 9 dBm. The phase noise of VCO is -90 dBc/Hz at 1-MHz offset. The total dc power dissipation of the transceiver is 142 mW and the size of the chip is only $1.2{\times}1.4mm^2$.

• 전기의세계
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• v.25 no.6
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• pp.69-73
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• 1976

Thd idle channel noise on FDM-microwave communication system is increasing because of the up-grade to wide-band loading. The thermal noise on receiver of microwave radio is measured according to their channel slot frequencies, low, meddle and high slots on the base band, from 60 channels to 960 channels. And suggested a consideration for system engineering, to reduce the thermal noise from radio microwave receivers, so as to improve signal to noise ratio.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.595-604
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• 2016

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.3
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• pp.34-38
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• 2000

This paper describes design, fabrication, and performance of an ultra-high-speed and low-noise MMIC (Monolithic Microwave Integrated Circuit) preamplifier for a 10 Gb/s optical receiver. The transimpedance type 3-stage MMIC preamplifier for ultra-high-speed and low-noise was designed using an AlGaAs/InGaAs/GaAs P-HEMTs(Pseudomorphic High Electron Mobility Transistors) with 0.15${\mu}{\textrm}{m}$ length T-shaped gate. To obtain broadband characteristics, we used the inductor peaking technique, and the gate width was optimized for low noise performance. Measurements reveal that the fabricated preamplifier has the high transimpedance gain of 60 ㏈Ω and 9.15 ㎓ bandwidth with the noise figure of less than 3.9 ㏈.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.647-653
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• 2005

According to the design concept of microwave front-end, a low noise amplifier block using HBT cascode topology is proposed to provide high gain and low noise figure with low bias current. We has implemented MMIC-LNA with a modified configuration using inductors to show low noise at the emitter and base of cascoded HBT-MMIC amplifier. The measured performance of the designed MMIC-LNA at 3.7GHz are a gain of 19dB, noise figure of 2.7dB and image rejection of 35dBc using a supply of 3mA and 2.7V. We can convinced that cascoded amplifier block to fulfill a high gain, low noise and image rejection if microwave front-end receiver is designed by cascode MMEC-LNA with the active image rejection filter.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.2
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• pp.93-100
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• 2008

In this paper, Low Noise Block down converter(LNB) is designed for a Ka-band satellite television receiver only(TVRO) using commercially available MMIC. Designed Low Noise Block down-converter is composed of three stage amplifiers involving input noise matched at first amplification stage, image reject band pass filter, frequency mixer and intermediate frequency amplification. Through LNB Module power budget to obtain gain and attenuation, Optimum LNB devices satisfying Ka-band LNB technical specification are selected. Experimental results of designed Ka-band LNB yields conversion gain of over $58{\pm}1dB$, noise figure of less than 1.5dB and phase noise of -94.6dBc @10KHz.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.305-308
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• 2009

This paper presents the design and analysis of RF Front End for Wireless Heartbeat measurement System. In this work LNA, an inductor connected at the gate of the cascode transistor and capacitive cross-coupling are strategically combined to reduce the noise and the nonlinearity influences of the cascode transistors in a differential LNA. The Mixer is implemented by using the Gilbert-type configuration, cross pmos injection technique and the resonating technique for the tail capacitance. The resulting LNA achieves 1.26 dB NF, better than 1.88dB NF Typical Also Mixer resulting achieves 9.8dB at 100KHz.