• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.894-897
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• 2003

Recently, the rapid growth of mobile radio system has led to an increasing demand of low-cost high performance communication IC's. In this paper, we have designed RF front end for wireless LAN receiver employ zero-IF architecture. A low-noise amplifier (LNA) and double-balanced mixer is included in a front end. The zero-IF architecture is easy to integrate and good for low power consumption, so that is coincided to requirement of wireless LAN. But the zero-IF architecture has a serious problem of large offset. Image-reject mixer is a good structure to solve offset problem. Using offset compensation circuit is good structure, too. The front end is implemented in 0.25 ${\mu}m$ CMOS technology. The front end has a noise figure of 5.6 dB, a power consumption of 16 mW and total gain of 22 dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.5
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• pp.426-429
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• 2017

For the W-band remote sensing radiometer, direct detection type radiometer receiver is designed. The receiver should be low noise and high gain of 60 dB unlike communication and radar receiver. The W-band radiometer consist of 4-stage low noise, high gain amplifier, band pass filter and square law detector. The developed direct detection receiver show 4 GHz bandwidth, 56 dB gain, and 4,500 mV/mW voltage sensitivity at integrator output port for -20 dBm input power at 94 GHz.

• ETRI Journal
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• v.46 no.4
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• pp.708-715
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• 2024

We propose a 10-GHz 2 × 2 phased-array radio frequency (RF) receiver with an 8-bit linear phase and 15-dB gain control range using 65-nm complementary metal-oxide-semiconductor technology. An 8 × 8 phased-array receiver module is implemented using 16 2 × 2 RF phased-array integrated circuits. The receiver chip has four single-to-differential low-noise amplifier and gain-controlled phase-shifter (GCPS) channels, four channel combiners, and a 50-Ω driver. Using a novel complementary bias technique in a phase-shifting core circuit and an equivalent resistance-controlled resistor-inductor-capacitor load, the GCPS based on vector-sum structure increases the phase resolution with weighting-factor controllability, enabling the vector-sum phase-shifting circuit to require a low current and small area due to its small 1.2-V supply. The 2 × 2 phased-array RF receiver chip has a power gain of 21 dB per channel and a 5.7-dB maximum single-channel noise-figure gain. The chip shows 8-bit phase states with a 2.39° root mean-square (RMS) phase error and a 0.4-dB RMS gain error with a 15-dB gain control range for a 2.5° RMS phase error over the 10 to10.5-GHz band.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.225-228
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• 2004

This paper has been studied about UWB(Ulra wide-band)'s LNA(Low Noise Amplifier) and Mixer. The UWB is a new technology that is being pursed for both commercial and military purposes. Direct conversion architectures that convert RF signals have potential to achieve such terminals, because they eliminate the need for non-programmable image-rejection filters and IF channel filters. And this architecture promises better performance in power, size, and cost than existing heterodyne - based receivers. This Receiver architectures combines low-noise amplifier, mixer. And then this paper has designed suitable UWB's LNA and Mixer.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.109-114
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• 2023

In this paper, a 2-channel Image-Reject receiver using a 65-nm CMOS process is presented for Ka-band compact radars. The designed receiver consists of Low-Noise Amplifier (LNA), IQ mixer, and Analog Baseband (ABB). ABB includes a complex filter in order to suppress unwanted images, and the variable gain amplifiers (VGAs) in RF block and ABB have gain tuning range from 4.5-56 dB for wide dynamic range. The gain of the receiver is controlled by on-chip SPI controllers. The receiver has noise figure of <15 dB, OP1dB of >4 dBm, image rejection ratio of >30 dB, and channel isolation of >45 dB at the voltage gain of 36 dB, in the Ka-band target frequency. The receiver consumes 420 mA at 1.2 V supply with die area of 4000×1600 ㎛.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.3
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• pp.282-288
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• 2014

In this paper, we have analyzed and designed a digital RF receiver based on the optimization of the dynamic range parameter to secure the wideband characteristics and linearity of digital radar receivers. To improve the wideband characteristics and dynamic range, a low noise amplifier is matching design with a noise source to minimize the noise figure in 1 GHz bandwidth and we improved the linearity of RF-receiver by securing the conversion gain characteristics of receiver through the design of active mixer. RF receiver is designed to give gain 63 dB, noise figure 1.2 dB and dynamic range of RF receiver has 75.8 dB in a wide band of 8.8~9.8 GHz. It is shown to be applicable to X-band digital radar receiver.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.115-120
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• 2005

A c-band microwave radiometer receiver for river mouth water temperature remote sensing was designed and implemented The developed receiver operated at 5.1GHz frequency with 70MHz bandwidth. It had high gain of 50dB and low noise figure of 2dB. Also we executed efficiency evaluation about detection capability of the receiver with noise source similar input signal. The experiment results showed that the c-band receiver successfully detected the antenna temperature range from 193K to 300K.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.1
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• pp.166-172
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• 2001

A RF wideband receiver for INMARSAT-B satellite communications system was composed of low noise amplifier and high gain amplifier, The low noise amplifier used to the resistive decoupling circuit for input impedance matching and self-bias circuits for low noise. The high gain amplifier consists of matched amplifier type to improve receiver gain. The active bias circuit can be used to provide temperature stability without requiring the large voltage drop or relatively high-dissipated power needed with a bias stabilization resistor. The bandpass filter was used to reduce a spurious level. As a result, the characteristics of the receiver implemented here show more than 60 dB in gain and less than 1.8:1 in input and output voltage standing wave ratio(VSWR), especially the carrier to noise ratio which is input signal level -126.7 dB m at 1537.5 MHz is a 45.23 dB /Hz at a 1.02 kHz.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.16-20
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• 2002

This paper describes the resistive FET mixer with low IF for the 4-Ch DBF(Digital Beam Forming) receiver with LNA(Low Noise Amplifier). This DBF receiver based on the direct conversion method is generally suitable for high-speed wireless mobile communications. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(IF) considered in this research are 2.09 ㎓, 2.08 ㎓ and 10㎒, respectively. The RF input power, LO input power and Vgs are used -10㏈m, 6㏈m and -0.4 V, respectively. In the 4-Ch resistive FET mixer with LNA, the measured IF and harmonic components of 10㎒, 20㎒, 2.09㎓ and 4.17㎓ are about -12.5 ㏈m, -57㏈m, -40㏈m and -54㏈m, respectively. The IF output power observed at each channel of 10㎒ is about -12.5㏈m and it is higher 27.5 ㏈m than the maximum harmonic component of 2.09㎓. Each IF output spectrum of the 4-Ch is observed almost same value and it shows a good agreement with the prediction.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.256-261
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• 2011

We demonstrate 3-Gb/s wireless link using a 60-GHz receiver front-end fabricated in $0.25-{\mu}m$ SiGe:C bipolar complementary metal oxide semiconductor (BiCMOS) and a mixed-mode quadrature phase-shift keying (QPSK) demodulator fabricated in 60-nm CMOS. The 60-GHz receiver consists of a low-noise amplifier and a down-conversion mixer. It has the peak conversion gain of 16 dB at 62 GHz and the 3-dB intermediate-frequency bandwidth of 6 GHz. The demodulator using 1-bit sampling scheme can demodulate up to 4.8-Gb/s QPSK signals. We achieve successful transmission of 3-Gb/s data in 60 GHz through 2-m wireless link.