• 한국컴퓨터산업학회논문지
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• 제2권7호
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• pp.895-904
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• 2001

본 연구에서는 능동 더블 밸런스 혼합기를 사용하기 때문에 이득을 높일 수 있지만 IIP3가 낮은 수신 시스템 I과 이득이 낮고 IIP3가 높은 수동 더블 밸런스 혼합기와 낮은 이득을 높이기 위한 중간 주파 증폭기로 구성된 수신 시스템II을 구성하여 수신 파라미터를 시험한 결과, 수신 시스템 I의 전체 잡음지수는 6.4382 dB이고 이득은 53.5dB, 제 3고조파 차단점은 -6.6352dB m이었다. 또한 수신 시스템II에서 전체 잡음지수는 9.70672dB이고 이득은 41dB, 제 3고조파 차단점은 3.66729dB m이었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.675-681
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• 2016

A 41dB gain control range $6^{th}$-order band-pass receiver front-end (RFE) using CMOS switched frequency translated impedance (FTI) is presented in a 40 nm CMOS technology. The RFE consists of a frequency tunable RF band-pass filter (BPF), IQ gm cells, and IQ TIAs. The RF BPF has wide gain control range preserving constant filter Q and pass band flatness due to proposed pre-distortion scheme. Also, the RF filter using CMOS switches in FTI blocks shows low clock leakage to signal nodes, and results in low common mode noise and stable operation. The baseband IQ signals are generated by combining baseband Gm cells which receives 8-phase signal outputs down-converted at last stage of FTIs in the RF BPF. The measured results of the RFE show 36.4 dB gain and 6.3 dB NF at maximum gain mode. The pass-band IIP3 and out-band IIP3@20 MHz offset are -10 dBm and +12.6 dBm at maximum gain mode, and +14 dBm and +20.5 dBm at minimum gain mode, respectively. With a 1.2 V power supply, the current consumption of the overall RFE is 40 mA at 500 MHz carrier frequency.

• ETRI Journal
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• 제46권4호
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• pp.708-715
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• 2024

We propose a 10-GHz 2 × 2 phased-array radio frequency (RF) receiver with an 8-bit linear phase and 15-dB gain control range using 65-nm complementary metal-oxide-semiconductor technology. An 8 × 8 phased-array receiver module is implemented using 16 2 × 2 RF phased-array integrated circuits. The receiver chip has four single-to-differential low-noise amplifier and gain-controlled phase-shifter (GCPS) channels, four channel combiners, and a 50-Ω driver. Using a novel complementary bias technique in a phase-shifting core circuit and an equivalent resistance-controlled resistor-inductor-capacitor load, the GCPS based on vector-sum structure increases the phase resolution with weighting-factor controllability, enabling the vector-sum phase-shifting circuit to require a low current and small area due to its small 1.2-V supply. The 2 × 2 phased-array RF receiver chip has a power gain of 21 dB per channel and a 5.7-dB maximum single-channel noise-figure gain. The chip shows 8-bit phase states with a 2.39° root mean-square (RMS) phase error and a 0.4-dB RMS gain error with a 15-dB gain control range for a 2.5° RMS phase error over the 10 to10.5-GHz band.

• 한국전자파학회논문지
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• 제20권9호
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• pp.900-905
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• 2009

본 논문에서는 전류 블리딩(bleeding)과 입력 인덕티브 직렬-피킹을 이용한 공통 드레인 귀환(Common Drain Feedback: CDFB) CMOS 광대역 저잡음 증폭기(Low Noise Amplifier: LNA)를 설계하였다. 캐스코드 증폭기와 귀환 증폭기를 DC 결합하여 블리딩 전류의 조정을 통해 LNA의 이득과 잡음 지수(Noise figure: NF)의 동적 제어를 실현하였다. 제작한 LNA는 2.5 GHz의 대역폭에서, 고이득 영역은 $1.7{\sim}2.8\;dB$ NF와 17.5 dB 이득, 그리고 27 mW의 전력 소비를 보이고, 저 이득 영역은 $2.7{\sim}4.0\;dB$ NF와 14 dB 이득, 그리고 1.8 mW의 전력 소비를 보인다.

• 한국양식학회지
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• 제11권1호
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• pp.39-48
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• 1998

Growth performance and excretions of nitrogen (N) and phosphorus (P) were investigated with carp (Cyprinus carpio) with carp (Cyprinus carpio) grower fed a low pollution diets (A and B) and commercial ones (Com-1 and Com-2). A recirculated rearing system (Exp. I) and a floating net cage system (Exp. II) were employed for two feeding trials in which fish having an initial body weight of 152g and 193g were fed for 41 an 39 days, respectively. The highest weight gain, daily growth rate and protein efficiency ratio were found (P<0.05) in fish fed diet A containing 10% fish meal and 2% monocalcium phosphate (MCP) for both experiments. They also showed the lowest feed conversion ratio and daily feeding ration among treatments. Fish fed diet B containing 10% fish meal, 5% fish protein concentrate and 1% MCP showed weight gain and FCR more improved (P<0.05) than those fed commercial diets. In all groups, whole body cmpositions were not greatly different among treatment, and protein and P contents in final fish ranged from 14.3 to 15.6% and from 0.39 to 0.48%, respectively. Fish fed diet A excreted the least N which were 38.3 in Exp. I and 39.6g/kg gain in Exp. II. However, the values found in fish fed two commercial diets amounted to 59.1 and 58.9g, respectively. A significant decrease in P excretion was also found in fish groups fed diets A and B. In Exp. I, a reduction of 53.4% was shown in fish fed diet A, compared to the averaged value (18.5g P/kg gain) of two commercial groups. In Exp. II conducted using the floating net cages, fish fed diet B excreted the least P (8.6g/kg gain) among the treatment, which was followed by fish fed diet A, showing 48.6% reduction compared to the average value (18.5g/kg gain) for fish fed two commercial diets. The present results clearly showed that N and P excretions from fish culture could be significantly reduced by using the low pollution diet.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.654-657
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• 2002

This paper introduces the design and implementation of 40-㎓-band low noise amplifier (LNA) with ultra low gain flatness for wide-band wireless multimedia and satellite communication systems. The 40-㎓-band 4-stage LNA MMIC (Monolithic Microwave Integrated Circuit) demonstrates a small signal gain of more than 20 ㏈, an input return loss of 10.3 ㏈, and an output return loss of 16.3 ㏈ for 37$\square$42 ㎓. The gain flatness of the 40-㎓-band 4-stage LNA MMIC was 0.1 ㏈ for 37$\square$42 ㎓. The noise figure of the 40 ㎓-band LNA was simulated to be less than 2.7 dB for 37~42 ㎓. The chip size of the 4-stage LNA MMIC was 3.7${\times}$1.7 $\textrm{mm}^2$.

• 한국전자파학회논문지
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• 제12권3호
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• pp.462-469
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• 2001

본 논문에서는 저주파 잡음이 상향변환 이득 해석을 이용한 K 밴드 국부발진기를 설계 및 제작하였다. 상향 변환 이득을 해석하고, 그에 따른 위상잡음을 예측하기 위하여 Two Signal Method(TSM)을 확장하였다. 제시된 이론의 유용성을 검증하기 위해 저 상향변환 이득을 갖는 회로의 동작점을 선택하여 free-running 발진기를 설계하였다. 측정결과 발진주파수는 23.42 GHz였고, 위상잡음은 1MHz offset에서 -105.2 dBc/Hz로 우수한 특성을 보였다. 그리고 같은 회로를 부고조파로 주입시켜 부고조파 주입동기 발진기로 동작시켰으며, 이 경우에도 낮은 부고조파 입력 파워에서 이상적인 체배기의 위상잡음 특성을 보였다.

• 대한전기학회논문지:전력기술부문A
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• 제48권4호
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• pp.461-466
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• 1999

A CMOS op amp with rail-to-rail input and output ranges is designed in a one-volt supply. The output stage of the op amp is used in a common source amplifier that operates in sub-threshold region to design a low voltage op amp with rail-to-tail output range. To drive heavy resistor and capacitor loads with rail-to-rail output ranges, a common source amplifier which has a low output resistance is utilized. A bulk-driven differential pair and a bulk-driven folded cascode amplifier are used in the designed op amp to increase input range and achieve 1 V operation. Post layout simulation results show that low frequency gain is about 58 ㏈ and gain bandwidth I MHz. The designed op amp has been fabricated in a 0.8${\mu}{\textrm}{m}$ standard CMOS process. The measured results show that this op amp provides rail-to-rail output range, 56㏈ dc gain with 1 MΩ load and has 0.4 MHz gain-bandwidth with 130 ㎊ and 1 kΩ loads.

• Journal of Power Electronics
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• 제18권1호
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• pp.11-22
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• 2018

This paper presents a single switch, high step-up, non-isolated dc-dc converter suitable for renewable energy applications. The proposed converter is composed of a coupled inductor, a passive clamp circuit, a switched capacitor and voltage lift circuits. The passive clamp recovers the leakage inductance energy of the coupled inductor and limits the voltage spike on the switch. The configuration of the passive clamp and switched capacitor circuit increases the voltage gain. A wide continuous conduction mode (CCM) operation range, a low turn ratio for the coupled inductor, low voltage stress on the switch, switch turn on under almost zero current switching (ZCS), low voltage stress on the diodes, leakage inductance energy recovery, high efficiency and a high voltage gain without a large duty cycle are the benefits of this converter. The steady state operation of the converter in the continuous conduction mode (CCM) and discontinuous conduction mode (DCM) is discussed and analyzed. A 200W prototype converter with a 28V input and a 380V output voltage is implemented and tested to verify the theoretical analysis.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.242-246
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• 2001

The alternated forward multi resonant converter (AT forward MRC) is studied on the transient response and the measured loop gain for stability. The compensator is composed of the error amplifier with 3 poles and 2 zeros. This is optimized through the experiment with HP4194A network analyzer. We are initiated by the thinking of how to make the stabilization from the experimental results of loop gain curves. The loop gain, low frequency gain and gain margin are more improved through the experimental considerations. Also, the transient response is more enhanced effectively.