• Korean Journal of Construction Engineering and Management
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• v.2 no.4 s.8
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• pp.48-61
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• 2001

This study aims at improving work reliability. It proposes a way to overcome the limitations of current scheduling methods by providing a new framework, CPAM(Construction Process Analysis Model) based on the lean principles. It suggests methods which improve work reliability and production effectiveness with variability control methods. Also it suggests methods which reduce inventories of materials and equipment and WIP(Work In Process) using two techniques; Lookahead Schedule and Weekly Work Plan. The contribution of this research also includes that it assumes planning as a process of reducing uncertainty and maximizing throughput, counter-posing plan reliability to resource redundancy as alternative strategies for managing in conditions of uncertain work flow.

• The Transactions of the Korea Information Processing Society
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• v.5 no.3
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• pp.774-784
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• 1998

본 논문은 현재 국내에서 개발되고 있는 광대역종합정보통신망(HAN/B-ISDN: HighlyAdvaned Network/Broadband Integrated Services Digital network)의 신호능력을 향상시키기 위한 요구 사항들과 정보 모델링에 관한 시나리오들을 제시하고 있다. 이러한 요구 사항들은 동등 대 동등과 계층 대 계층 신호 프로토콜에 사용될 수 있으며, 신호 능력 향상에 EK른 B-ISDN 연결형 베어러 서비스들은 Sb/Tb 참조 점에서 연결된 둘 또는 그 이상의 파티들 사이에서 B-ISDN 가상 경로, 가상 채널, 또는 공통 루트 연결 그룹 연결을 통하여 사용자 정보의 전달을제한 없이 제공할 수 있다 또한 본 논문에서는 현재 적용되고 있는 국내 B-ISDN에서 신호 능력을 향상 시키는 방안으로써 호 관련 정보 흐름을 정보 모델링을 통하여 제안한다. 본 논문을 통하여 지속적으로 작성되고 개발되는 모든 국내 B-ISDN 장치들이 단계별로 보다 충실할 수 있고, 추후 NNI에서의 신호 방식 호 절차를 통한 광대역 텔레 서비스를 처리할 수 있으며, 단말 사용자에게는 최대한의 편의를 제공할 수 있을 것이다.

• International Journal of Internet, Broadcasting and Communication
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• v.11 no.4
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• pp.31-36
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• 2019

Unsupervised neural networks have not caught enough attention until Generative Adversarial Network (GAN) was proposed. By using both the generator and discriminator networks, GAN can extract the main characteristic of the original dataset and produce new data with similarlatent statistics. However, researchers understand fully that training GAN is not easy because of its unstable condition. The discriminator usually performs too good when helping the generator to learn statistics of the training datasets. Thus, the generated data is not compelling. Various research have focused on how to improve the stability and classification accuracy of GAN. However, few studies delve into how to improve the training efficiency and to save training time. In this paper, we propose a novel optimizer, named FAST-ADAM, which integrates the Lookahead to ADAM optimizer to train the generator of a semi-supervised generative adversarial network (SSGAN). We experiment to assess the feasibility and performance of our optimizer using Canadian Institute For Advanced Research - 10 (CIFAR-10) benchmark dataset. From the experiment results, we show that FAST-ADAM can help the generator to reach convergence faster than the original ADAM while maintaining comparable training accuracy results.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.62-65
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• 2011

FPGA는 대용량의 게이트를 지원하는 하드웨어를 프로그램 할 수 있는 디바이스이다. ASIC을 위해 설계된 로직은 칩으로 제조되기 전에 검증 과정을 거친다. 이 검증 과정에서 시뮬레이션의 한계를 극복하기 위해 FPGA를 사용한 에뮬레이션 방법을 많이 채택한다. 에뮬레이션 과정에서 ASIC의 동작 속도로 검증하는 것이 바람직하지만 FPGA의 특성상 ASIC과 같은 속도로 동작하기는 쉽지 않은 것이 현실이다. 본 논문에서는 HDL 코딩 방법에 따른 FPGA의 성능 민감도를 실험하였다. 실험 및 평가를 위해 다양한 알고리즘을 가진 가산기를 이용하였고 각 가산기 종류와 비트수에 따라 Verilog-HDL을 이용하여 코딩하였으며 대표적인 FPGA 제조사(Altera와 Xilinx)별, 디바이스별로 동작 속도와 자원 사용량을 측정하였다. 실험 결과 FPGA 제조사별로 다른 경향을 보임을 확인하였다. 성능 면에서는 비트별로 다소 차이는 있지만 Altera 디바이스에서는 Ripple Carry, Carry Lookahead 가산기보다 Prefix 가산기의 성능이 우수하게 나왔다. Xilinx 디바이스에서는 예상과 달리 가산기들 사이의 성능 차이가 크게 나지 않았으며 Ripple Carry, Carry Lookahead 가산기가 Prefix 가산기보다 높은 성능을 보이는 경우도 있었다. 비용 면에서는 디바이스별로 큰 차이가 나지 않았으며 ASIC과 비슷한 성능 민감도를 보였다. 그리고 각 제조사에서 제공하는 IP(Intellectual Property) Core를 사용했을 경우는 대부분의 디바이스에서 우수한 성능을 보여 주었다. TSMC 90nm 공정 기술로 제작한 ASIC과 IP Core를 비교했을 때는 ASIC의 성능이 4배 정도 우수한 것으로 나타났다.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.843-846
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• 1998

산술연산을 수행하는 가산기는 ALU(arithmetic logic unit)의 성능을 좌우하는데 매우 중요한 역할을 하며, 어떠한 캐리 생성 방식을 사용하는냐에 따라 그 성능이 결정될 수 있다. RCA(Ripple carry adder)는 간단하고, 쉬운 설게로 널리 사용되자만, 캐리의 전파지연 문제로 인해 고속의 가산기 응용에의 부적합하다. 또한, CLA(carry lookahead adder)방식의 가산기는 캐리의 지연시간이 가산기의 단수와 무관하므로, 연산속도를 높일 수 있는 장점이 있지만 더하고자 하는 bit의 수가 클수록 회로가 매우 복잡해지는 큰 단점을 가지고 있다. 따라서, 본 논문에서는 간단하면서도 성능이 우수한 64bit 가산기를 설계하고 시뮬레이션을 통하여 설계된 회로의 우수성을 증명하였다.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.5
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• pp.10-17
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• 1993

This paper suggests a new addition algorithm. A circuit to implement the algorithm and the result of its performance evaluation are presented. The basic idea of the algorithm is that to obtain the sum of two operands, two operands bits are exclusive-ORed and then the result is inverted by the carry from the previous stage. An unique carry prediction method minimizes carry propagation. The proposed circuit has a very simple and regular structure compared with CLA (carry lookahead adder). It also requires less gates for the implementation about 50% and operates faster.

• The Journal of the Acoustical Society of Korea
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• v.18 no.7
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• pp.33-38
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• 1999

In this paper, we combine a generalized analysis-by-synthesis (AbS) structure and an algebraic excitation scheme to propose a new 4kb/s speech codec. This codec partly uses the structure of G.729. We design a line spectrum pair (LSP) quantizer, an adaptive codebook, and an excitation codebook to fit the 4 kb/s bit rate. The codec has a 25㎳ algorithmic delay, which corresponds to a 20㎳ frame size and a 5㎳ lookahead. At the bit rates below 4kb/s, most CELP speech codecs using the AbS principle have a drawback that results a rapid degradation of speech quality. To overcome this drawback we use the generalized AbS structure which is efficient for the low bit rate speech codec. LP coefficients are converted to LSP and quantized using a predictive 2-stage VQ. A low complexity algebraic codebook which uses shifting method is used for the fixed codebook excitation, and gains of the adaptive codebook and the fixed codebook are quantized using the VQ. To evaluate the performance of the proposed codec A-B preference tests are done with the fixed rate 8kb/s QCELP. As the result of the test, the performance of the codec is similar to that of the fixed rate 8kb/s QCELP.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.176-184
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• 2005

In this paper, we implemented an Elliptic Curve Cryptography(ECC) processor for Digital Transmission Contents Protection (DTCP), which is a standard for protecting various digital contents in the network. Unlikely to other applications, DTCP uses ECC algorithm which is defined over GF(p), where p is a 160-bit prime integer. The core arithmetic operation of ECC is a scalar multiplication, and it involves large amount of very long integer modular multiplications and additions. In this paper, the modular multiplier was designed using the well-known Montgomery algorithm which was implemented with CSA(Carry-save Adder) and 4-level CLA(Carry-lookahead Adder). Our new ECC processor has been synthesized using Samsung 0.18 m CMOS standard cell library, and the maximum operation frequency was estimated 98 MHz, with the size about 65,000 gates. The resulting performance was 29.6 kbps, that is, it took 5.4 msec to process a 160-bit data frame. We assure that this performance is enough to be used for digital signature, encryption and decryption, and key exchanges in real time environments.

• Journal of Korea Multimedia Society
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• v.11 no.5
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• pp.703-709
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• 2008

The methodology of the compiler construction improved by well-defined parsing techniques and developments of automatic generation tools. Through them, a variety of compilers for the special applications can be developed effectively: particularly, the compiler for embedded/mobile devices. Also, as contents industry is proliferating recently, the necessity of developing a compiler which is suitable for contents system is highly increasing. These various demands can be resolved by modular techniques and automatic construction of compilers. But, optimization of compiler itself as development tools uses heuristic methods and it needs higher cost. In this paper, we suggest the parsing method which can decrease unnecessary reduce actions by analyzing the characteristics of LR parser. The suggested parsing technique uses lookahead/ states, reachable reduction goals information in parsing process and enhances the parsing efficiency by changing continuous reduce actions to one. Actually, we applied it to the front-end of ANSI C compiler and proved the parsing performance in terms of the number of reduce actions.

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• 2008.11a
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• pp.252-255
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• 2008

The purpose of construction project management is to achieve planned quality by adequate cost and schedule of the project, thus the effective time management is a critical factor to actualize the object. But the traditional time management by using milestone has several limitations which are not sufficiently considered mutual relation and variated from the task. On this wise, applying the concept and principles of lean construction to the project will be the best way not only reduce waste and variation, but also improve the productivity and ability to overcome limitation as mentioned above. Thus the study, Last Planner System, specially focuses on constraint analysis which is used in lookahead planning system. The results of this research will provide the constraints classification that is able to improve work reliable and percent plan complete when time planning by controlling constraints of project.