• Title/Summary/Keyword: log processor

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A Single Channel Speech Enhancement for Automatic Speech Recognition

  • Lee, Jinkyu;Seo, Hyunson;Kang, Hong-Goo
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2011.07a
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    • pp.85-88
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    • 2011
  • This paper describes a single channel speech enhancement as the pre-processor of automatic speech recognition system. The improvements are based on using optimally modified log-spectra (OM-LSA) gain function with a non-causal a priori signal-to-noise ratio (SNR) estimation. Experimental results show that the proposed method gives better perceptual evaluation of speech quality score (PESQ) and lower log-spectral distance, and also better word accuracy. In the enhancement system, parameters was turned for automatic speech recognition.

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A Study on the Multiple Fault-Tolerant Multipath Multistage Interconnection Network (다중 고정이 허용되는 다중경로 다단상호접속망에 관한 연구)

  • 김대호;임채택
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.8
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    • pp.972-982
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    • 1988
  • In multiprocessor systems, there are Omega network and M network among various MIN's which interconnect the processor and memory modules. Both one-path Omega network and two-path M network are composed of Log2N stages. In this paper, Augmented M network (AMN) with 2**k+1 paths and Augmented Omega network (AON) with 2**k paths are proposed. The proposed networks can be acomplished by adding K stage(s) to M network and Omega network. Using destination tag, routing algorithm for AMN and AON becomes simple and multiple faults are tolerant. By evaluating RST(request service time) performance of AMN and AON with (Log2N)+K stages, we demonstrated the fact that MMIN (AMN) with 2**k+1 paths performs better than MMIN(AON) with 2**k+1. paths.

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Virtual-Parallel Multistage Interconnection Network with multiple-paths (다중경로를 갖는 가상병렬 다단계 상호연결 네트워크)

  • Kim, Ik-Soo
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.1
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    • pp.67-75
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    • 1997
  • This paper presents a virtual-parallel multistage interconnection network (MIN) which provides multipath between processor and memory module. The proposed virtual-parallel MIN network which uses $m{\times}1$ mutiplexer at the input switching block, $1{\times}m$ demultiplexer at the output switching block and logN-1 switching stages has maximum $2{\times}m$ unique paths between processor and memory module. Because it has multi-redundance paths, a number of processors can connect a specific Also, this new virtual-parallel structured MIN network can reduce packet collision possibility at switching block and it has cost. It shown to improve a performance and to be a very simple structure in comparision with MBSF structured MIN.

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A Hierarchical Deficit Round-Robin Algorithm for Packet Scheduling (패킷 스케쥴링을 위한 결손 보완 계층적 라운드로빈 알고리즘)

  • Pyun Kihyun;Cho Sung-Ik;Lee Jong-Yeol
    • Journal of KIISE:Information Networking
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    • v.32 no.2
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    • pp.147-155
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    • 2005
  • For the last several decades, many researches have been performed to distribute bandwidth fairly between sessions. In this problem, the most important challenge is to realize a scalable implementation and high fairness simultaneously. Here high fairness means that bandwidth is distributed fairly even in short time intervals. Unfortunately, existing scheduling algorithms either are lack of scalable implementation or can achieve low fairness. In this paper, we propose a scheduling algorithm that can achieve feasible fairness without losing scalability. The proposed algorithm is a Hierarchical Deficit Round-Robin (H-DRR). While H-DRR requires a constant time for implementation, the achievable fairness is similar to that of Packet-by-Packet Generalized Processor Sharing(PGPS) algorithm. PGPS has worse scalability since it uses a sorted-priority queue requiring O(log N) implementation complexity where N is the number of sessions.

Efficient Transformations Between an $n^2$ Pixel Binary Image and a Boundary Code on an $n^3$ Processor Reconfigurable Mesh ($n^3$ 프로세서 재구성가능 메쉬에서 $n^2$ 화소 이진영상과 경계코드간의 효율적인 변환)

  • Kim, Myung
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.8
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    • pp.2027-2040
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    • 1998
  • In this paper, we present efficient reconfigurable mesh algorithms for transforming between a binary image and its corresponding boundary code. These algorithms use $n\timesn\timesn$ processors when the size of the binary image is $n\timesn$. Recent published results show that these transformations can be done in O(1) time using $O(n^4)$ processors. The number of processors used by these algorithms is very large compared to the number of pixels in the image. Here, we present fast transformation algorithms which use $n^3 processors only. the transformation from a houndary code to a binary image takes O(1) time, and the converse transformation takes O(log n) time.

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A study of extended processor trace decoder structure for malicious code detection (악성코드 검출을 위한 확장된 프로세서 트레이스 디코더 구조 연구)

  • Kang, Seungae;Kim, Youngsoo;Kim, Jonghyun;Kim, Hyuncheol
    • Convergence Security Journal
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    • v.18 no.5_1
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    • pp.19-24
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    • 2018
  • For a long time now, general-purpose processors have provided dedicated hardware / software tracing modules to provide developers with tools to fix bugs. A hardware tracer generates its enormous data into a log that is used for both performance analysis and debugging. Processor Trace (PT) is a new hardware-based tracing feature for Intel CPUs that traces branches executing on the CPU, which allows the reconstruction of the control flow of all executed code with minimal labor. Hardware tracer has been integrated into the operating system, which allows tight integration with its profiling and debugging mechanisms. However, in the Windows environment, existing studies related to PT focused on decoding only one flow in sequence. In this paper, we propose an extended PT decoder structure that provides basic data for real-time trace and malicious code detection using the functions provided by PT in Windows environment.

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Speech Recognition System for Home Automation Using DSP (DSP를 이용한 홈 오토메이션용 음성인식 시스템의 실시간 구현)

  • Kim I-Jae;Kim Jun-sung;Yang Sung-il;Kwon Y.
    • Proceedings of the Acoustical Society of Korea Conference
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    • autumn
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    • pp.171-174
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    • 2000
  • 본 논문에서는 홈 오토메이션 시스템을 음성인식을 도입하여 설계하였다. 많은 계산량과 방대한 양의 데이터의 처리를 요구하는 음성인식을 DSP(Digital Signal Processor)를 통하여 구현해 보고자 본 연구를 수행하였다. 이를 위해 실시간 끝점검출기를 이용하여 추가의 입력장치가 필요하지 않도록 시스템을 구성하였다. 특징벡터로는 LPC로부터 유도한 10차의 cepstrum과 log 스케일 에너지를 이용하였고, 음소수에 따라 상태의 수를 다르게 구성한 DHMM(Discrete Hidden Marcov Model)을 인식기로 사용하였다. 인식단어는 가정 자동화를 위하여 많이 쓰일 수 있는 10개의 단어를 선택하여 화자 독립으로 인식을 수행하였다. 또한 단어가 인식이 되면 인식된 단어에 대해서 현재의 상태를 음성으로 알려주고 이에 대해 자동으로 실행하도록 시스템을 구성하였다.

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Event Logging Method for Control Rod Control System (원자로 제어봉구동장치 제어시스템용 이벤트 기록 방법)

  • Cheon, Jong-Min;Kim, Choon-Kyung;Jo, Chang-Hui;Jeong, Soon-Hyun;Nam, Jeong-Han
    • Proceedings of the KIEE Conference
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    • 2003.11c
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    • pp.552-554
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    • 2003
  • This paper is about the method by which Power Control Unit(PCU) of Control Rod Control System(CRCS) logs events in the system and the real-time monitoring display. This method enables the functions like the event logging of Control Rod Drive Mechanism(CRDM)/power Cabinet, the off-line show of the event data logged and the on-line show by communication between the PCU and the monitoring display. Operators in a nuclear power plant must be able to grasp any possible abnormal states correctly. Because our newly designed system has a good ability to log and display the kinds, tine, and the prior and posterior states of urgent or non-urgent events, the operators can judge, maintain and repair the abnormal event more easily.

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Efficient RMESH Algorithms for Computing the Intersection and the Union of Two Visibility Polygons (두 가시성 다각형의 교집합과 합집합을 구하는 효율적인 RMESH 알고리즘)

  • Kim, Soo-Hwan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.2
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    • pp.401-407
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    • 2016
  • We can consider the following problems for two given points p and q in a simple polygon P. (1) Compute the set of points of P which are visible from both p and q. (2) Compute the set of points of P which are visible from either p or q. They are corresponding to the problems which are to compute the intersection and the union of two visibility polygons. In this paper, we consider algorithms for solving these problems on a reconfigurable mesh(in short, RMESH). The algorithm in [1] can compute the intersection of two general polygons in constant time on an RMESH with size O($n^3$), where n is the total number of vertices of two polygons. In this paper, we construct the planar subdivision graph in constant time on an RMESH with size O($n^2$) using the properties of the visibility polygon for preprocessing. Then we present O($log^2n$) time algorithms for computing the union as well as the intersection of two visibility polygons, which improve the processor-time product from O($n^3$) to O($n^2log^2n$).

Signal Processing for Speech Recognition in Noisy Environment (잡음 환경에서 음성 인식을 위한 신호처리)

  • Kim, Weon-Goo;Lim, Yong-Hoon;Cha, Il-Whan;Youn, Dae-Hee
    • The Journal of the Acoustical Society of Korea
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    • v.11 no.2
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    • pp.73-84
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    • 1992
  • This paper studies noise subtraction methods and distance measures for speech recognition in a noisy environment, and investigates noise robustness of the distance measures applied to the problem of isolated word recognition in white Gaussian and colored noise (vehicle noise) environments. Noise subtraction methods which can be used as a pre-processor for the speech recognition system, such as the spectral subtraction method, autocorrelation subtraction method, adaptive noise cancellation and acoustic beamforming are studied, and distance measures such and Log Likelihood Ratio ($d_{LLR}$), cepstral distance measure ($d_{CEP}$), weighted cepstral distance measure ($d_{WCEP}$), spectral slope distance measure ($d_{RPS}$) and cepstral projection distance measure ($d_{CP},\;d_{BCP},\;d_{WCP},\;d_{BWCP}$) are also investigated. Testing of the distance measures for speaker-dependent isolated word recognition in a noisy environment indicate that $d_{RPS}\;and\;d_{WCEP}$ which weigh higher order cepstral coefficients more heavily give considerable performance improvement over $d_{CEP}and\;d_{LLR}$. In addition, when no pre-emphasis is performed, the recognizer can maintain higher performance under high noise conditions.

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