• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 추계학술대회
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• pp.225-228
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• 2012

본 논문은 8-비트 디코더, 2-비트 시간-인터폴레이터, 그리고 출력 버퍼로 구성된 10-비트 시간-인터폴레이션 디지털-아날로그 변환기를 제안한다. 제안하는 시간-인터폴레이션 기법은 RC 로우패스 필터에 의한 시정수를 이용해서 charging time을 조절하여 아날로그 값을 결정하는 방법이다. 또한 시간-인터폴레이터를 구현하기 위해 공정 변화를 최소화하기 위해 레플리카 회로를 포함한 제어 펄스 발생기를 제안한다. 제안하는 10-비트 시간-인터폴레이션 디지털-아날로그 변환기는 3.3 V $0.35{\mu}m$ 1-poly 6-metal CMOS 공정을 이용하여 설계된다. 설계된 10-비트 시간-인터폴레이션 디지털-아날로그 변환기의 면적은 기존의 10-비트 저항열 디지털-아날로그 변환기의 61%를 차지한다. 그리고 시뮬레이션 된 DNL과 INL은 각각 +0.15/-0.21 LSB와 +0.15/-0.16 LSB이다.

• 전자공학회논문지B
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• 제29B권8호
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• pp.54-65
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• 1992

A huge amount of multiplications is required for 2-D filtering on the image data, making it difficult to implement a real-time quincuncial interpolator. In this paper, efficient design technique and VLSI structures for 2-D multipleierless filter are presented. In the filter design, by introducing an efficient scheme for discretizing the frequency response of the prototype filter, it is shown that a significant amount of the computational burden required in the conventional techniques, such as local search, branch and bound techniques, could be saved. In the case of 5$\times$5 filter, it is found that the design technique described in this paper could save about 80% of the computation time, compared to the conventional methods, while providing a comparable performance. For a hardware implementation, two different VLSI structures for 2-D multiplierless filter are also introduced in the paper : One is for block parallel processing and the other for scan-line parallel processing. In both structure, the AP(area-period) figure improves over Wu's structure[4].

• 전자공학회논문지S
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• 제35S권2호
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• pp.114-125
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• 1998

In this study, for the first time, we propose the ADI(Adaptive De-Interlacing) algorithm, which improves visually and subjectively, horizontal and vertical edges on the image processed by the ELA (Edge Based Line Average) method. The proposed ADI algorithm enlargesthe window size to 5*3 in order to utilize the feature of the continuity of edges, and the adaptive interpolator is employed to decide adaptiely horizontal, diagonal, and vertical edges. Based on the results of the compter simulation, it is confimed that the new ADI algorithm improve the PSNR by 0.5dB in the Lena image with 512*512 size and by 0.4dB in the sequence image of a salesman, respectively. For the horizontal and vertial edges on the still and salesman sequence images, the proposed ADI algorithm has better visulal improvement than the conventional ELA algorithm.

• 한국기계가공학회지
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• 제10권3호
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• pp.33-38
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• 2011

A cubic spline trajectory planner with arc-length parameter is formulated with estimation by summing up to the 3rd order in Taylor's expansion. The PVAJT motion planning is presented to reduce trajectory calculation time at every cycle time of servo control loop so that it is able to generate cubic spline trajectory in real time. This method can be used to more complex spline trajectory. Several case studies are executed with different values of cycle time and sampling time, and showed the advantages of the PVAJT motion planner. A DSP-based motion controller is designed to implement the PVAJT motion planning.

• 한국농공학회:학술대회논문집
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• 한국농공학회 2002년도 학술발표회 발표논문집
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• pp.289-292
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• 2002

In this study, a topography based hydrologic model (TOPMODEL) was tested on the Anseong-cheon watershed. Pit in watershed was removed by liner trend surface interpolator. The DTM Analysis program is used to derived a distribution of ln($a/tan{\beta}$) values from DEM (Digital Elevation Model) using the MDF (Multiple Direction Flow) algorithm of Quinn et al (1995). Current TOPMODEL program limits are number of time step, ln($a/tan{\beta}$) increment, delay histogram ordinate and size of subcatchment pixel maps. Therefore, TOPMODEL is not suitable for application of large watershed. Muskingum method and watershed division enhance grid pixel resolution for rainfall-runoff simulation accuracy.

• 한국군사과학기술학회지
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• 제4권2호
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• pp.30-41
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• 2001

In Underwater Flight Vehicle depth control system, the followings must be required. First, It needs a robust performance which can get over the nonlinear characteristics due to hull shape. Second, It needs an accurate performance which has the small overshoot phenomenon and steady state error to avoid colliding with ground surface and obstacles. Third, It needs a continuous control input to reduce the acoustic noise. Finally, It needs an effective interpolation method which can reduce the dependency of control parameters on speed. To solve these problems, we propose a Intelligence depth control method using Fuzzy Sliding Mode Controller and Neural Network Interpolator. Simulation results show the proposed control scheme has robust and accurate performance by continuous control input and has no speed dependency problem.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1996년도 한국자동제어학술회의논문집(국내학술편); 포항공과대학교, 포항; 24-26 Oct. 1996
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• pp.656-659
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• 1996

An universal NURBS interpolation for an open architectured CNC controller is proposed in order to unify internal data structure and algorithm of different interpolations such as linear, circular and spline, and to intelligently interface CAD database of the various workpiece contour. Furthermore, NURBS interpolation may result in better surface roughness and high speed machining due to the continuous generation of cutter movement. The mathematical manipulation of NURBS is presented and the practical implementation on the CNC controller of a lathe is discussed for real machining. The comparison between a computer design and workpieces machined on a lathe shows the feasibility of the NURBS interpolation format as an universal interpolation scheme.

• 대한전자공학회논문지TC
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• 제49권8호
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• pp.33-38
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• 2012

본 논문은 DVB-T2 시스템에서 잡을 효과를 최소화시키기 위한 등화 알고리즘이 제안한다. 제안알고리듬은 동일한 시간영역 OFDM 심볼 내에서 신호 구간 선택을 달리하여 예측한 채널응답과 주파수 영역의 데이터를 평균하여 성능을 개선한다. 컴퓨터모의 실험을 통하여 제안알고리듬의 성능을 기존 알고리듬과 비교 평가한다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2002년도 ICCAS
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• pp.121.1-121
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• 2002

Calculation unit and peripheral units that are used to make the position controller are embedded to one chip FPGA. $\textbullet$ Feed-forward PID controller and interpolator in the calculation unit mitigate frequent context switching. $\textbullet$ The peripheral units reduce the size of the joints position control board. $\textbullet$ Because the calculation unit is designed with pipeline structure, it has the advantages to apply to the multi joints.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.860-863
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• 2002

Realizations of multirate converters are proposed using periodically time-varying (PTV) structures. By exploiting the computational redundancy of the filtering operation in a multirate filter, it is possible to implement the filter with much less hardware. In the proposed implementations, several coefficients time-share in a periodic fashion the hardware of one multiply-and-add. Therefore, each multiply-and-add circuit performs different coefficient scalings at different time instants within a period. Compared to the direct form realization, the proposed realizations reduce the hardware of an interpolator and a decimator by a factor of approximately U and M, respectively, while retaining the same processing speed, where U and M are the upsampling and downsampling factors, respectively. The approach can be used to obtain realizations for sampling rate conversion by a rational factor of U/M, where U and M are relatively prime, in which case hardware reduction by a factor of approximately UM can be achieved.