• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2007.06a
• /
• pp.157-158
• /
• 2007

• Journal of Biomedical Engineering Research
• /
• v.28 no.6
• /
• pp.803-810
• /
• 2007

Although synthetic aperture focusing techniques can improve the spatial resolution of ultrasound imaging, they have not been employed in a commercial product because they require a real-time N-channel beamformer with a tremendously increased hardware complexity for simultaneous beamforming along M multiple lines. In this paper, a hardware-efficient beamformer architecture for synthetic aperture focusing is presented. In contrast to the straightforward design using NM delay calculators, the proposed method utilizes only M delay calculators by sharing the same values among the focusing delays which should be calculated at the same time between the N channels for all imaging points along the M scan lines. In general, synthetic aperture beamforming requires M 2-port memories. In the proposed beamformer, the input data for each channel is first upsampled with a 4-fold interpolator and each polyphase component of the interpolator output is stored into a 2-port memory separately, requiring 4M 2-port memories for each channel. By properly limiting the area formed with the synthetic aperture focusing, the input memory buffer can be implemented with only 4 2-port memories and one short multi-port memory.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.6
• /
• pp.594-600
• /
• 2015

A 1.25 GHz multi-phase phase-rotating PLL is proposed for oversampling CDR applications and implemented with a low power and small area. Eight equidistant clock phases are simultaneously adjusted by the phase interpolator inside the PLL. The phase interpolator uses only two complementary clocks from a VCO, but it can cover the whole range of phase from $0^{\circ}$ to $360^{\circ}$ with the help of a PFD timing controller. The output clock phases are digitally adjusted with the resolution of 25 ps and both INL and DNL are less than 0.44 LSB. The proposed PLL was implemented using a 110 nm CMOS technology. It consumes 3.36 mW from 1.2 V supply and occupies $0.047mm^2$. The $jitter_{rms}$ and $jitter_{pk-pk}$ of the output clock are 1.91 ps and 18 ps, respectively.

• Journal of information and communication convergence engineering
• /
• v.13 no.4
• /
• pp.235-240
• /
• 2015

A decimation chain for multi-standard reconfigurable radios is presented for 900-MHz and 1,900-MHz dual-band cellular standards with a data interpolator based on the Lagrange method for adjusting the variable data rate to a fixed data rate appropriate for each standard. The two proposed configurations are analyzed and compared to provide insight into aliasing and the signal bandwidth by means of a newly introduced measure called interpolation error. The average interpolation error is reduced as the ratio of the sampling frequency to the signal BW is increased. The decimation chain and the multi-rate analog-to-digital converter are simulated to compute the interpolation error and the output signal-to-noise ratio. Further, a method to operate the above-mentioned chain under a compressed mode of operation is proposed in order to guarantee continuous packet connectivity for inter-radio-access technologies. The presented decimation chain can be applied to LTE, WCDMA, GSM multi-mode multi-band digital front-end which will ultimately lead to the software-defined radio.

• ETRI Journal
• /
• v.33 no.3
• /
• pp.366-373
• /
• 2011

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2002.05a
• /
• pp.574-577
• /
• 2002

In this paper, we propose a new symbol time synchronization scheme suitable for the OFDM system with an interpolator. The proposed performs the following three steps. In the first step, the coarse symbol time synchronization is achieved by continuously measuring the average power of the received envelope signal. Based on this average power, the detection possibility for the symbol time synchronization is determined. If the signal is sufficient for synchronization, we next perform a relatively accurate symbol time synchronization by measuring the correlation a short training signal and the received envelope signal. Finally, an additional frequency synchronization is performed with a long training signal to correct symbol synchronization errors caused by the phase rotation. From the simulation results, one can see that the proposed synchronization scheme provides a good synchronization performance over frequency selective channels.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.4B
• /
• pp.237-244
• /
• 2003

This paper presents the design of a QPSK/16-QAM downstreams receiver chip. The proposed chip consists of a blind equalizer, a timing recovery block and a carrier recovery block. The blind equalizer uses a DFE sturucture using CMA(Constant Module Algorithm). The symbol timing recovery uses the modified parabolic interpolator. The decision-directed carrier recovery is used to remove the carrier frequency offset, phase offset and phase jitter. The implemented LMDS receiver can support four data rates, 10, 20, 30 and 40 Mbps and can accommodate the symbol rate up to 10 Mbaud. This symbol rate is faster than existing QAM receivers.

• Journal of the Korean Society for Precision Engineering
• /
• v.16 no.11
• /
• pp.197-203
• /
• 1999

Increasing demands on precision machining have necessitated the tool to move not only position error as small as possible, but also with smoothly varying feedrates. Because of the lack of accurate and efficient algorithms for generation of 3-dimensional lines and circles, a full accomlishment for available machine tool resolution is generally unavailable. In this paper, a reference-pulse type 3-axis PC_NC milling system is developed for the precision machining of complex shapes in 3-dimensional space. Three AC servomotors are used as the actuator instead of the hand wheel to operate a 3-axis milling machine under the same mechanical structure. A PC is used to handle the control signal calculation for various types of motion command. To achieve the synchronous 3-axis motion, a real-time reference-pulse 3-dimensional linear and circular interpolator based on the intersection criteria is developed in software. The performance test via computer simulation and actual machining have shown that the PC-NC milling system is useful for the machining of arbitrary lines and circles in 3-dimensional space.

• Journal of the Korean Society for Precision Engineering
• /
• v.16 no.9
• /
• pp.172-178
• /
• 1999

3D linear and circular interpolations are a basic part for the machining of complex shapes. Until now, because of the absence of appropriate algorithms for the generation of 3D lines and circles, a full accomplishment for available machine tool resolution is difficult. this paper presents new algorithms for 3D linear and circular interpolation in the reference pulse technique. In 3D space, the line or circle is not expressed as an implicit function, it is only defined as the intersection of two surfaces. A 3D line is defined as the intersection of two planes, and a 3D circle is defined as the intersection of a plane and the surface of a sphere. Based on these concepts, interpolation algorithms are designed to follow intersection curves in 3D space, and a real-time 3D linear and circular interpolator was developed in software using a PC. The algorithm implemented in a PC showed promising results in interpolation error and speed performance. It is expected that it can be applied to the next generation computerized numerical control systems for the machining of 3D lines, circles and some other complex shapes.

• Transactions of the Korean Society of Mechanical Engineers
• /
• v.12 no.5
• /
• pp.968-975
• /
• 1988

The maximum feedrate generated from the hardware DDA is closely related to its calculation efficiency. The smaller interpolation span results in the lower calculation efficiency. This paper presents the method to improve the calculation efficiency for the smaller interpolation span. For the linear interpolation the higher calculation efficiency can be achieved by putting biggest value that the interpolation DDA can hold. for the circular interpolation, however, the scheme used for linear interpolation does not work since arbitrary change of value in the interpolation DDA changes the radius of the circle. The bit length of the hardware DDA is adjusted instead of adjusting the value in DDA, which results in the every same effect on calculation efficiency for the circular interpolation. The hardware circuit and supporting software are designed, and tested by two axis step motor driven milling machine. The experimental results show that the proposed method drastically increases the maximum feedrate even for the smaller interpolation span.