• Title/Summary/Keyword: interpolator

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Design and Implementation of the Modified Cubic Interpolator Based on Variable Parameters for Multi-Band OFDM UWB System (Multi-Band OFDM UWB 시스템용 변형된 가변 파라미터를 이용한 큐빅 인터폴레이터의 설계 및 구현)

  • Kim, Sang-Dong;Lee, Jong-Hum;Jung, Woo-Young;Chong, Jong-Wha
    • IEMEK Journal of Embedded Systems and Applications
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    • v.1 no.1
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    • pp.20-23
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    • 2006
  • 본 논문은 MB-OFDM UWB(Multi Band-Orthogonal Frequency Division Multiplexing Ultra Wide Band) 시스템을 위한 변형된 가변 파라미터를 이용한 큐빅 인터폴레이터를 제안한다. MB-OFDM UWB 시스템은 고속의 동작속도가 필요하기 때문에, 기존 가변 파라미터를 이용한 큐빅 인터폴레이터에 병렬 처리 기술과 파이프라인 기법을 동시에 적용한다. 실험 결과, Stratix II 2S60F101020C3 디바이스를 타켓으로 최대지연경로 속도와 최대지연경로 주기가 각각 최대 88.79MHz와 11.262ns가 되었고, 동작속도는 최대 대략 200% 이상 향상되었음을 알 수 있다.

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Design of the Fuzzy Sliding Mode Controller and Neural Network Interpolator for UFV Depth Control

  • Kim, Hyun-Sik;Park, Jin-Hyun;Choi, Young-Kiu
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.176.2-176
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    • 2001
  • In Underwater Flight Vehicle depth control system, the followings must be required. First, it needs robust performance which can get over nonlinear characteristics. Second, it needs accurate performance which have small overshoot phenomenon and steady state error. Third, it needs continuous control input. Finally, it needs interpolation method which can solve the speed dependency problem of controller parameters. To solve these problems, we propose adepth control method using Fuzzy Sliding Mode Controller and Neural Network Interpolator. Simulation results show the proposed method has robust and accurate control performance by the continuous control input and has no speed dependency problem.

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Real-time Line Interpolation of a NURBS Curve based on the Acceleration and Deceleration of a Servo Motor (서보 모터의 가감속을 고려한 NURBS 곡선의 실시간 직선 보간)

  • 이제필;이철수
    • Proceedings of the Korean Society of Machine Tool Engineers Conference
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    • 2001.04a
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    • pp.405-410
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    • 2001
  • In this paper, a new parametric curve interpolator is proposed based on a 3D(3-dimensional) NURBS curve. A free curve is generally divided into small linear segments or circular arcs in CNC machining. The method has caused to a command error, the limitation of machining speed, and the irregular machining surface. The proposed real-time 3D NURBS interpolator continuously generates a linear segment within the range of allowable acceleration/deceleration in the motion controller. Therefore, the algorithm calculates the curvature and the remained distance of a command curve for the smoothing machining. It is expected to attaining high speed and high precision machining in CNC Machine Tool.

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Cross-coupled Control with a New Contour Error Model (새로운 윤곽 오차 모델을 이용한 상호 결합 제어)

  • 이명훈;손희수;양승한
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1997.10a
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    • pp.341-344
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    • 1997
  • The higher precision in manufacturing field is demanded, the more accurate servo controller is needed. To achieve the high precision, Koren proposed the cross-coupled control (CCC) method. The objective of the CCC is reducing the contour error rather than decreasing the individual axial error. The performance of CCC depends on the contour error model. In this paper we propose a new contour error model which utilizes contour error vector based on parametric curve interpolator. The experimental results show that the new CCC is more accurate than the variable-gain CCC during free-form curve motion.

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Parametric NURBS Curve Interpolators: A Review

  • Mohan, Sekar;Kweon, Sung-Hwan;Lee, Dong-Mok;Yang, Seung-Han
    • International Journal of Precision Engineering and Manufacturing
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    • v.9 no.2
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    • pp.84-92
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    • 2008
  • Free-form shapes which were once considered as an aesthetic feature are now an important functional requirement. CNC industries are looking for a compact solution for reproducing free-form shapes as conventional interpolation models are inadequate, The parametric curve interpolator developed in the last decade has clearly emerged as favorite among its contemporaries in recent years, At present intense research has been done on parametric curve interpolators and interesting developments are reported. Out of the various parametric representations for curves and surfaces, NURBS has been standardized and widely used in free-form shape design. This paper presents a review of various methods of parametric interpolation for NURBS and discusses the salient features, problems and solutions. Recent approaches on variable feedrate interpolation, parameter compensation are also reviewed and research trends are addressed finally.

Study on the Performance Comparision of Software Pulse Interpolators (소프트웨어 펄스 보간기의 성능비교)

  • Ahn, J.H.;Lim, H.S.;Lee, W.K.
    • Journal of the Korean Society for Precision Engineering
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    • v.13 no.9
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    • pp.62-69
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    • 1996
  • Interpolator is a very important element in NC machines in that it controls tool path and speed. In this paper, studied were extensive interpolation characteristics of reference pulse method among various interpolation and pulse generation methods. Specifically, processing speed and path error of DDA, SPD and SFG methods were compared and analyzed against line, circle and elipse. As a result, in the point of processing speed, SPD method was found to be the best for line interpolation, SFG method for circle and ellipse, and DDA method was found to be the slowest for all paths. In the point of path error, DDA method was found to have the biggest error for all kinds of paths.

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A Simple Phase Interpolator based Spread Spectrum Clock Generator Technique (간단한 위상 보간기 기반의 스프레드 스펙트럼 클락 발생 기술)

  • Lee, Kyoung-Rok;You, Jae-Hee;Kim, Jong-Sun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.10
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    • pp.7-13
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    • 2010
  • A compact phase interpolator (PI) based spread spectrum clock generator (SSCG) for electromagnetic interference (EMI) reduction is presented. The proposed SSCG utilizes a digitally controlled phase interpolation technique to achieve triangular frequency modulation with less design complexity and small power and area overhead. The novel SSCG can generate the system clock with a programmable center-spread spectrum range of up to +/- 2 % at 200 MHz, while maintaining the clock duty cycle ratio without distortions. The PI-based SSCG has been designed and evaluated in 0.18-um 1.8-V CMOS technology, which consumes about 5.0 mW at 200MHz and occupies a chip size of $0.092mm^2$ including a DLL.

A CDR using 1/4-rate Clock based on Dual-Interpolator (1/4-rate 클록을 이용한 이중 보간 방식 기반의 CDR)

  • Ahn, Hee-Sun;Park, Won-Ki;Lee, Sung-Chul;Jeong, Hang-Geun
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.46 no.1
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    • pp.68-75
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    • 2009
  • In this paper, an efficient proposed CDR(Clock and Data Recovery Circuits) using 1/4-rate clock based on dual-interpolator is proposed. The CDR is aimed to overcome problems that using multi-phase clock to decrease the clock generator frequency causes side effects such as the increased power dissipation and hardware complexity, especially when the number of channels is high. To solve these problems, each recovery part generates needed additional clocks using only inverters, but not flip-flops while maintaining the number of clocks supplied from a clock generator the same as 1/2-rate clock method. Thus, the reduction of a clock generator frequency using 1/4-rate clocking helps relax the speed limitation and power dissipation when higher data rate transfer is demanded.

A 125 MHz CMOS Delay-Locked Loop with 64-phase Output Clock (64-위상 출력 클럭을 가지는 125 MHz CMOS 지연 고정 루프)

  • Lee, Pil-Ho;Jang, Young-Chan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.259-262
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    • 2012
  • This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.

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Nonuniform Delayless Subband Filter Structure with Tree-Structured Filter Bank (트리구조의 비균일한 대역폭을 갖는 Delayless 서브밴드 필터 구조)

  • 최창권;조병모
    • The Journal of the Acoustical Society of Korea
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    • v.20 no.1
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    • pp.13-20
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    • 2001
  • Adaptive digital filters with long impulse response such as acoustic echo canceller and active noise controller suffer from slow convergence and computational burden. Subband techniques and multirate signal processing have been recently developed to improve the problem of computational complexity and slow convergence in conventional adaptive filter. Any FIR transfer function can be realized as a serial connection of interpolators followed by subfilters with a sparse impulse response. In this case, each interpolator which is related to the column vector of Hadamard matrix has band-pass magnitude response characteristics shifted uniformly. Subband technique using Hadamard transform and decimation of subband signal to reduce sampling rate are adapted to system modeling and acoustic noise cancellation In this paper, delayless subband structure with nonuniform bandwidth has been proposed to improve the performance of the convergence speed without aliasing due to decimation, where input signal is split into subband one using tree-structured filter bank, and the subband signal is decimated by a decimator to reduce the sampling rate in each channel, then subfilter with sparse impulse response is transformed to full band adaptive filter coefficient using Hadamard transform. It is shown by computer simulations that the proposed method can be adapted to general adaptive filtering.

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