• 전자공학회논문지B
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• 제30B권7호
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• pp.14-23
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• 1993

This paper proposes an algorithm to reduce the bitrate for transmission of MCP(motion compensated prediction) error signals. Many digital image coders have recently employed hybrid coding schemes which perform motion compensation, DCT transform, quantization, and variable length coding. The variable length coding compresses the quantized DCT coefficient data by removing their statistical redundancy. But some DCT blocks have the interblock statistical redundancy as well as the intrablock one. To utilize both of them, the DCT blocks are classified into the interleaving group and the non-interleaving group. And then each DCT blocks in the interleaving group are is encoded independently, and the DCT blocks in the interleaving group are encoded after interleaving the DCT coefficients. Through the simulations, it is shown that the proposed method outperforms the conventional method in which each DCT block is encoded independently.

• 한국통신학회논문지
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• 제31권5C호
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• pp.497-502
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• 2006

본 논문에서는 디지털 컨텐츠의 저작권 보호를 위해 기존의 고정된 셔플링 테이블을 이용한 암호화의 가장 큰 단점인 평문 공격에 대한 취약성을 보완할 수 있는 암호화 기법을 제안하였다. 이를 위해 우선, 영상의 특징 값에 따라 적응적으로 변하는 인터리빙 방법을 제안하고 제안된 인터리빙 방법만을 사용하여 DPCM 처리된 $8^*8$블록을 셔플링하는 암호화 방법과 인터리빙과 기존의 랜덤 셔플링 방법을 결합한 다중 셔플링 방법을 이용하여 영상을 암호화하는 두 가지 방법을 제안하였다. 모의 실험 결과 제안한 두 가지 셔플링 방법을 이용한 암호화 방법은 영상의 국소적인 특징 값에 따라 적응적으로 변하기 때문에 기존의 고정된 형태의 랜덤 셔플링 테이블만을 사용하는 방법에 비해 평문 공격에 강인한 특징을 가졌고 또한 추가적인 비트량 증가도 발생하지 않는 장점을 보였다.

• 한국통신학회논문지
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• 제24권12B호
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• pp.2424-2429
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• 1999

본 논문은 길쌈 부호화 (convolutional encoding) 및 인터리빙(interleaving) 기법을 사용하는 채널 부호기에 있어서 메모리 크기를 최소화한 설계 방법에 관한 것이다. 기존의 구현방식에서는 프레임 데이터를 보관하는 입력버퍼 RAM과 인터리빙을 위한 인터리버 RAM을 별도로 사용해야 한다. 본 논문에서는 메모리 크기가 큰 인터리버 RAM을 사용하는 대신 입력버퍼 RAM 1개를 추가로 사용하여 길쌈 부호화 및 인터리빙을 동시에 처리할 수 있는 새로운 채널 부호기 설계 방법을 제안하였다. 이 설계 방법을 여러 디지털 이동통신 모뎀의 채널 부호기에 적용한 결과 기존 설계 방식에 비해 33% ∼60%의 메모리 크기 감소 효과가 있었으며, 프레임 데이터 수신 시 처리 절차가 간편해지고 타이밍 마진을 늘일 수 있는 장점이 있었다.

• Journal of Power Electronics
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• 제19권6호
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• pp.1515-1526
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• 2019

Ear-piercing high-frequency noise from electromagnetic vibrations in motors has become unacceptable in sensitive environments, due to the application of pulse width modulation (PWM) and in consideration of switching losses. This paper proposed a synchronous periodic frequency modulation (SPFM) method based on the interleaving technique for paralleled three-phase voltage source inverters (VSIs) to eliminate PWM vibration noise. The proposed SPFM technique is able to effectively remove unpleasant high-frequency vibration noise as well as acoustic noise more effectively than the conventional periodic carrier frequency modulation (PCFM) and interleaving technique. It completely eliminates the vibration noise near odd-order carrier frequencies and reduces the PWM vibration noise near even-order carrier frequencies depending on the switching frequency variation range. Furthermore, the SPFM method is simple to implement and does not employ additional circuits in the drive system. Finally, the effectiveness of the proposed method has been confirmed by detailed experimental results.

• 전기전자학회논문지
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• 제16권2호
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• pp.153-158
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• 2012

A new diversity combining scheme is proposed for time-of-arrival (TOA) estimation of chirp signal in dense multipath channel. In the multipath channel, the performance of TOA estimation using conventional correlation matrix-based diversity combining scheme is degraded due to the lack of de-correlation effect. To increase the de-correlation effect, the proposed diversity scheme employs interleaving method based on the property of de-chirped signal. As a result, the proposed scheme increases de-correlation effect and also reduces the noise of TOA estimation. Finally, the diversity achieved from the proposed scheme improves TOA estimation performance. The de-correlation effect is analyzed mathematically. The estimation accuracy of the proposed diversity scheme is superior to that of conventional diversity scheme in multipath channel.

• Journal of Electrical Engineering and Technology
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• 제10권5호
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• pp.1983-1988
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• 2015

This paper proposes the enhanced application of superconducting magnetic energy storage (SMES) for the effective compensation of power fluctuations based on the interleaving technique. With increases in demand for renewable energy based photovoltaic (PV) generation system, the output power fluctuations from PV generation system due to sudden changes in environmental conditions can cause serious problems such as grid voltage and frequency variations. To solve this problem, the SMES system is applied with its superior characteristics with respect to high power density, fast response for charge and discharge operations, system efficiency, etc. In particular, the compensation capability is effectively improved by the proposed interleaving technique based on its parallel structure. The dynamic performance of the system designed using the proposed method is evaluated with several case studies through time-domain simulations.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권5호
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• pp.445-454
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• 2015

As the feature sizes and the operating charges continue to be scaled down, multi-bit soft errors are becoming more critical in SRAM designs of a few nanometers. In this paper, we propose an efficient error detection technique to reduce the size of parity bits by applying a 2D bit-interleaving technique to 3D bit-partitioned SRAM devices. Our proposed bit-interleaving technique uses only 1/K (where K is the number of dies) parity bits, compared with conventional bit-interleaving structures. Our simulation results show that 1/K parity bits are needed with only a 0.024-0.036% detection error increased over that of the existing bit-interleaving method. It is also possible for our technique to improve the burst error coverage, by adding more parity bits.

• 한국산학기술학회논문지
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• 제10권8호
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• pp.1832-1838
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• 2009

본 논문은 레이더의 펄스반복주기(PRI)를 포함한 각종 파라메타들을 비교하여 주파수 급속변경 레이더 신호를 식별하는 전자전 장비의 알고리즘에 관한 연구이다. 일반적으로 레이더는 단일주파수의 반송파를 사용하여 표적을 탐지하여 왔으나 최신 레이더들은 전자보호 기능을 강화하기 위해서 주파수 급속변경 반송파를 많이 사용하고 있다. 단일 주파수 사용 레이더 신호들이 전자전 장비에 수신되면, 전자전 장비는 레이더의 방위, 주파수, 펄스폭을 분석하여 레이더의 위치와 종류를 식별하였다. 그러나 주파수 급속변경 레이더인 경우에는 주파수가 비주기적으로 변경되므로 주파수를 레이더의 식별요소로 사용하는 것이 부적당하다. 따라서 본 논문에서는 Linked-List and Queue 방식으로 레이더 신호 요소들을 배치하여 레이더의 PRI를 구한 후에, PRI를 포함한 다수 파라메타들을 비교하여 주파수 급속변경 레이더를 식별하는 방법을 제안하였다. 제안된 알고리즘은 주파수 급속변경 레이더 신호를 포함한 레이더 신호의 분리가 매우 양호하였다.

• ETRI Journal
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• 제26권5호
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• pp.375-383
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• 2004

This paper proposes a common interleaving method associated with independent channel-encoding among transmitter antenna branches in orthogonal frequency and code division multiplexing based on multiple-input multiple-output (MIMO) multiplexing to achieve an extremely high throughput such as 1 Gbps using a 100 MHz bandwidth. This paper also investigates the average packet error rate performance as a function of the average received signal energy per bit-to-background noise power spectrum density ratio $(E_b/N_0)$. We found that the loss in the required average received $E_b/N_0$ of the proposed method is only within approximately 0.3 dB in up to a 12-path Rayleigh fading channel, using 16QAM and Turbo coding with a coding rate of 5/6. We also clarify that even for a large fading correlation among antenna branches, 1 Gbps is still possible by increasing the transmission power. Therefore, the proposed method reduces the processing rate to 1/4 in the turbo decoder with only a slight loss in the required average received $E_b/N_0$.

• Journal of Power Electronics
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• 제10권2호
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• pp.132-137
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• 2010

Interleaving techniques are widely used to reduce input/output ripples and to increase the power capacity of boost converters operating in critical conduction mode. Two types of phase-shift control schemes are studied in this paper, the turn-on time shifting method and the turn-off time shifting method. It is found that although the turn-off time shifting method exhibits better performance, it suffers from sub-harmonic oscillations at high input voltages. To solve this problem, an intensive quantitative analysis of the sub-harmonic oscillation phenomenon is made in this paper. Based upon that, a novel modified turn off time shifting control scheme for interleaved boost converters operating in critical conduction mode is proposed. An important advantage of this scheme is that both the master phase and the slave phase can operate stably in critical conduction mode without any oscillations in the full input voltage range. This method is implemented with a FPGA based digital PWM control platform, and tests were carried out on a two-phase interleaved boost PFC converter prototype. Experimental results demonstrated the feasibility and performance of the proposed phase-shift control scheme.