• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.963_964
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• 2009

This paper presents an output ripple reduction of Active-Clamp Forward Converter, which is mainly composed of interleaving two active-clamping forward converters. By interleaving, Output ripple is reduced. The leakage inductance of the transformer or an additional resonant inductance is employed to achieve ZVS during the dead times. The duty cycles are not limited to be equal and within 50%. The complementary switching and the resulted interleaved output inductor currents diminish the current ripple in output capacitors. Accordingly, the smaller output chokes and capacitors lower the converter volume and increase the power density. Detailed analysis of this ouput reduction of Active-Clamp Forward Converter is described.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1009_1010
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• 2009

This paper presents a power supply system with pre-regulator using zero voltage switching (ZVS) interleaving two-transistor forward converter for high input voltage and high power application. A SMPS has a advantage that a good efficiency, small size and light weight but has a noise problem. A linear power supply system has a advantage that a good stability, low ripple and noise but has a disadvantage that a big size, low efficiency and heat problem. To alleviate these problems, we propose an power supply system using dual ZVS interleaving two-transistor forward pre-regulator. The proposed converter is verified on a 1kW, 50kHz experimental prototype.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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• pp.547-550
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• 2004

An interleaved single-stage power-factor-correction (PFC) AC/DC converter is presented in this paper. The proposed converter is combined by two single-stage AC/DC converters based on flyback converter Each PFC stage operates in discontinuous conduction mode (DCM). By exploiting the interleaving technique, the input ripple current and output ripple voltage are reduced. The proposed converter complied with EN/1EC61000-3-2 harmonic regulations achieves high efficiency and low cost. The performance of the proposed converter was evaluated on a 180W $(90W\times2,\;24V,\;7.5A)$ experimental prototype.

• Journal of Communications and Networks
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• 제5권2호
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• pp.174-183
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• 2003

Space-Time (ST) codes are known to provide high transmission rates, diversity and coding gains. In this paper, a tight upper bound on the error probability of ST codes over rapid fading channels is presented. Moreover, ST codes suitable for rapid fading channels are presented. These codes are designed using the QPSK and 16-QAM signal constellations. The proposed codes are based on two different encoding schemes. The first scheme uses a single trellis encoder, whereas the second scheme uses the I-Q encoding technique. Code design is achieved via partitioning the signal space such that the design criteria are maximized. As a solution for the decoding problem of I-Q ST codes, the paper introduces a low-complexity decoding algorithm. Results show that the I-Q ST codes using the proposed decoding algorithm outperform singleencoder ST codes with equal complexity. The proposed codes are tested over fading channels with different interleaving conditions, where it is shown that the new codes are robust under such imperfect interleaving conditions.

• 전기전자학회논문지
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• 제24권2호
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• pp.586-591
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• 2020

본 논문에서는 인터리브된 전류 주입형 고승압 DC-DC 컨버터가 제안된다. 높은 전압 이득 외에도 인터리빙 방식을 채택하여 낮은 리플 입력 전류가 달성된다. 또한 제안 된 컨버터의 소프트 스위칭 특성은 전력 스위치의 스위칭 손실을 줄이고 변환 효율을 높인다. 변압기의 누설 인덕턴스를 활용하여 다이오드의 전류 변화율을 제어함으로써 출력 정류기의 역 회복 문제도 완화된다. 200W 프로토 타입에서 얻은 실험 결과에 대해 설명한다.

• 전자공학회논문지A
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• 제32A권4호
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• pp.24-31
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• 1995

In this paper, the dual-mode burst-error-correcting decoding algorithm is adapted to the multiple trellis-coded .pi./4 shift QPSK in order to achieve the improvement of bit error rate (BER) performance over fading channels. The dual-mode adaptive decoder which combines maximum likelihood decoding with a burst detection scheme usually operates as a Viterbi decoder and switches to time diversity error recovery whenever an uncorrectable error pattern is identified. Rayleigh fading channels and Rician fading channels having the Rician parameter K=5dB are used in computer simulation, and the simulation results are compared with those of interleaving techniques. It is shown that under the constraint of the fixed overall memory quantity, the dual-mode adaptive decoding scheme gains an advantage in the BER performance with respect to interleaving strategies.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 I
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• pp.97-100
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• 2003

The quasi-complementary turbo codes (QCTC) proposed by Kim [1] is used for a fast hybrid ARQ scheme with incremental redundancy and adaptive modulation coding in the cdma2000 1xEV-DV [2]. The QCTC provides various code rates with good performance, a very simple encoder structure, and an inherent channel interleaving. It is shown that the QCTC is a unified scheme of channel coding and channel interleaving. In this paper, we introduce the properties of QCTC and various hybrid ARQ-QCTC schemes for the system.

• 한국항행학회논문지
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• 제15권2호
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• pp.227-233
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• 2011

본 논문에서는 저면적 ISDB-T 시간 디인터리버 구조를 제안하였다. ISDB-T는 일본과 중남미에서 많이 사용되고 있는 이동형 TV 표준으로써 긴 인터리빙을 이용하여 다른 표준에 비해 높은 성능을 보이고 있다. 그러나 긴 인터리빙을 구현하기 위해서는 많은 지연 버퍼가 필요하다. 지연 버퍼들은 주소 레지스터가 있어야 하므로 주소 레지스터의 개수도 많아진다. 본 논문에서는 디인터리버의 등가 변환을 통해 주소 레지스터의 개수를 크게 줄이는 구조를 제안하였다. 실험 결과를 통해 디인터리버의 면적을 줄일 수 있음을 확인할 수 있었다.

• Journal of Electrical Engineering and Technology
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• 제5권3호
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• pp.435-442
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• 2010

This paper proposes an 18-step back-to-back (BTB) voltage source converter using four sets of 3-Level converter modules with auxiliary circuits to increase the number of steps. The proposed BTB voltage source converter has the independent control capability of active power and reactive power at the interconnected ac system. The operational feasibility of the proposed BTB converter was verified through many simulations with PSCAD/EMTDC software. The feasibility of hardware implementation was verified through experimental results with a scaled hardware prototype. The proposed BTB converter could be widely applied for interconnecting the renewable energy source to the power grid.

• ETRI Journal
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• 제28권5호
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• pp.672-675
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• 2006

The effect of block interleaving in a low density parity check (LDPC)-turbo concatenated code is investigated in this letter. Soft decoding can be used in an LDPC code unlike the conventional Reed-Solomon (RS) code. Thus, an LDPC-turbo concatenated code can show better performance than the conventional RS-turbo concatenated code. Furthermore, the performance of an LDPC-turbo code can be improved by using a block interleaver between the LDPC and turbo code. The average number of iterations in LDPC decoding can also be reduced by a block interleaver.