• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.885-888
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• 2005

In this study, we designed an ARM9 compatible RISC microprocessor using VHDL. The microprocessor was designed to support Harvard architecture with separate instruction cache and data cache. The state machine was optimized for multi-cycle instructions. In addition, a data forwarding mechanism was adopted to reduce the stall cycles due to data hazards. Assembly programs were up-loaded into a ROM block for system-level simulation. Proper operation of the designed microprocessor was confirmed by investigating the contents of the internal registers as well as the RAM block. Futhermore, the simulation results clearly indicated that the operation speed of the processor designed in this study is enhanced by reducing the execution cycles required for multiplication related instructions.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1003-1006
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• 2005

Vertex shader of GPU in personal computer is advanced in functions as to be half of traditional fixed T&L functions. And, capacity of memory for saving resources to process instructions is unlimited. GPU that can be programmed by programmer is needed for mobile system as well as personal computer. In this paper, we implement software virtual machine for vertex shader using C++ Language. Our goal is designing hardware GPU that can apply to mobile system. The virtual machine consists of nVidia GPU instructions. Input Data to virtual machine is generated by Microsoft fxc compiler. That is to say, Input Data is compiled shader program written in HLSL, Cg, or ASM. The virtual machine will be a reference model for designing hardware GPU and can be used for Testbed to test added or modified instruction.

• Journal of Korean Institute of Industrial Engineers
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• v.20 no.1
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• pp.71-85
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• 1994

Overhead cranes which carry heavy items in construction or production areas consist of structure and electric modules. More than 80% of breakdowns bring out of the electric module. As operators do not know all about cranes, it sometimes takes much time to repair the cranes. In order to resolve this problem, the expert system which can diagnose causes of faults and give instructions for repair to operators, has been developed. The scope of the paper is limited to the electric module. First of all, analyzing symptoms and causes, we have developed a rule base with the expert system shell, EXSYS. Furthermore, for the facility maintenance including repair instructions against the causes, the instruction data base was developed with FOXPRO. On the other hand, for the help of user's understanding the fault causes, the graphic animation module which shows malfunctioning component ports or motions in 3D was developed with the graphic software, TOPAS VGA.

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.350-353
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• 2007

This paper presents an real-time implementation of H.264/AVC High 4:4:4 Predictive profile decoder using general-purpose processors by exploiting multi-threading technique and Single Instruction Multiple Data (SIMD) instructions without any quality degradation. We analyze differences between the existing High profile and High 4:4:4 Predictive profile decoder, and show various optimization techniques to decode high fidelity and high definition (HD) video in real-time. Simulation results show that the proposed decoder can play high fidelity HD video at average 40 frames per seconds (fps) for the IBBrBP bistream and about 50 fps for the Intra-only bitstream.

• THE INTERNATIONAL COMMERCE & LAW REVIEW
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• v.24
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• pp.73-104
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• 2004

This paper intends to prevent dangerous goods shipments from compromising safety, and to minimize the risks to life and property inherent in air transport of dangerous goods. For this purpose, this paper reviews the changes of international standards for the international air transport of dangerous goods, and recommends the methods for improving the management system for the air transport of dangerous goods. As for the research methodology, this paper reviews the current regulations of the ICAO Technical Instructions for the Safe Transport of Dangerous Goods, IATA Dangerous Goods Regulations, and national regulations governing the air transport of dangerous goods in Korea. As the results of this paper, it is anticipated that the national regulations for shipping dangerous goods by air will be detailed, and compliance with the regulations will be enforced. In conclusion, ensuring the safe transport of dangerous goods by air is a shared responsibility of the government authorities, carriers and shippers.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.141-151
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• 1994

this paper describes the design and implementation of a RISC processor for embedded control systems. This RISC processor integrates a register file, a pipelined execution unit, a FPU interface, a memory interface, and an instruction prefetcher. Its characteristics include both single cycle executions of most instructions in a 2 phase 20 MHz frequency and the worst case interrupt latency of 7 cycles with the vectored interrupt handling that makes it possible to be applicable to the real time processing system. For efficient handling of multi-cycle instructions, data stationary hardwired control scheme equippedwith cycle counter was used. This chip integrates about 139K transistors and occupies 9.1mm$\times$9.1mm in a 1.0um DLM CMOS technology. The power dissipation is 0.8 Watts from a 5V supply at 20 MHz operation.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.269-272
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• 2001

In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.228-231
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• 1999

This paper describes the design and implementation of an application specific instruction-set processor developed for embedded DSP applications. The instruction-set has an uniform size of 16 bits, and supports 3 types of instructions: Primitive, Complex, and Specific. To reduce code size and cycle count we introduce complex instructions that can be selected according to the application under consideration, which leads to 50% code size reduction maximally. The processor has two independent data memories to double the data throughput and the address space. The processor is synthesized by 0.6$\mu$m single-poly double-metal technology. Critical path simulation shows that the maximum frequency is 110MHz and total gate count is 132, 000.

• ETRI Journal
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• v.34 no.5
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• pp.787-790
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• 2012

The objective of this research is to design a high-performance NAND flash memory system containing a buffer system. The proposed instruction buffer in the NAND flash memory consists of two parts, that is, a fully associative temporal buffer for temporal locality and a fully associative spatial buffer for spatial locality. A spatial buffer with a large fetching size turns out to be effective for serial instructions, and a temporal buffer with a small fetching size is devised for branch instructions. Simulation shows that the average memory access time of the proposed system is better than that of other buffer systems with four times more space. The average miss ratio is improved by about 70% compared with that of other buffer systems.

• Journal of Korean Home Economics Education Association
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• v.4 no.1
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• pp.1-15
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• 1992

The aim of the research is to develop a PC based courseware which is programed to drafts clothing patterns. The pattern making are numerically formulized. The of the program were as follows；1. Menu and instructions are displayed in Korean Language. 2. Easy step-by-step instructions explaining how to draw basic pattern and design pattern. 3. Low cost personal computer and general purpose printer are used. The source program was written in C-language and compiled using Turbop C. The Bezier spline is used to draw curves of pattern and to display Korean characters and pattern on same screen simultaneoulsy, Korean characters are drawn graphically. The low cost IBM Personal Computer or compatibles with Hercules Graphic Card is required to run this grogram.