• Journal of the Korean Magnetics Society
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• v.14 no.1
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• pp.52-57
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• 2004

In this research, characteristics of air core rectangular spiral type inductors of ㎓ band are numerical analyzed. The basic structure of inductors is a rectangular spiral having 390${\mu}{\textrm}{m}$${\times}$390${\mu}{\textrm}{m}$ size, 5.5 turns, line width of 10 ${\mu}{\textrm}{m}$ and line space of 10 ${\mu}{\textrm}{m}$. Frequency characteristics were simulated up to 10 ㎓. The substrate was modeled as Si, Sapphire, glass and GaAs and the conductor as Cu. The thickness of the conductor was fixed at 2. The number of turns was n.5 to make the input and output terminals to be on the opposite sides. The initial inductance of the basic inductor structure was 13.0 nH, maximum inductance 60.0 nH and resonance frequency 4.25 ㎓. As the dielectric constant of the substrate was increased, the initial inductance varied only slightly, but the resonance frequency decreased considerably. As the number of turns was varied from 1.5 to 9.5, the initial inductance was increased linearly from 2.9 nH to 15.9 nH and, then, saturated at 16.9 nH. The Q factor increased only slightly. The line width and line space of inductors were varied from 5 ${\mu}{\textrm}{m}$ to 20 ${\mu}{\textrm}{m}$, which resulted in the decrease of the initial and maximum inductances. But the resonance frequency was increased. Q factor displayed an increase and a decrease, respectively, when the line width and line space were increased.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.7
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• pp.38-45
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• 2006

The superconducting fault current limiters(SFCLs) provide the effect such as enhancement in power system reliability due to limiting the fault current within a few miliseconds. Among various SFCLs we have developed a flux-lock type SFCL and exploited a special design to effectively reduce the fault current according to properly adjustable magnetic field after the short-circuit test. This SFCL consists of two copper coils wound in parallel on the same iron core and a component using the YBCO thin film connected in series to the secondary copper coil. Meanwhile, operating characteristics can be controlled by adjusting the inductances and the winding directions of the coils. To analyze the operational characteristics, we compared closed-loop with open-loop iron core. When the applied voltage was 200[Vrms] in the additive polarity winding, the peak values of the line current the increased up to 30.71[A] in the closed-loop and 32.01[A] in the open-loop iron core, respectively. On the other hand, in the voltages generated at current limiting elements were 220.14[V] in the closed-loop and 142.73[V] in the opal-loop iron core during first-half cycle after fault instant under the same conditions. We confirmed that the open-loop iron core had lower power burden than in the closed-loop iron core. Consequently, we found that the structure of iron core enabled the flux-lock type SFCL at power system to have the flexibility.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.6-13
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• 2009

For X-band phased array systems, a power amplifier, a 6-bit phase shifter, a 6-bit digital attenuator, and a SPDT transmit/receive (T/R) switch are fabricated and measured. All circuits are demonstrated by using CMOS 0.18 um technology. The power amplifier has 2-stage differential and cascade structures. It provides 1-dB gain-compressed output power ($P_{1dB}$) of 20 dBm and power-added-efficiency (PAE) of 19 % at 8-11 GHz frequencies. The 6-bit phase shifter utilizes embedded switched filter structure which consists of nMOS transistors as a switch and meandered microstrip lines for desired inductances. It has $360^{\circ}$ phase-control range and $5.6^{\circ}$ phase resolution. At 8-11 GHz frequencies, it has RMS phase and amplitude errors are below $5^{\circ}$ and 0.8 dB, and insertion loss of $-15.7\;{\pm}\;1,1\;dB$. The 6-bit digital attenuator is comprised of embedded switched Pi-and T-type attenuators resistive networks and nMOS switches and employes compensation circuits for low insertion phase variation. It has max. attenuation of 31.5 dB and 0.5 dB amplitude resolution. Its RMS amplitude and phase errors are below 0.4 dB and $2^{\circ}$ at 8-11 GHz frequencies, and insertion loss is $-10.5\;{\pm}\;0.8\;dB$. The SPDT T/R switch has series and shunt transistor pairs on transmit and receive path, and only one inductance to reduce chip area. It shows insertion loss of -1.5 dB, return loss below -15 dB, and isolation about -30 dB. The fabricated chip areas are $1.28\;mm^2$, $1.9mm^2$, $0.34\;mm^2$, $0.02mm^2$, respectively.