• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.107-108
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• 2007

In order to investigate the electrical properties of Hf-silicate as a function of annealing temperature, Hf-silicate deposited by atomic layer deposition (ALD) was studied. After Hf-silicate film deposition, annealing was proceeded at $500^{\circ}C\;and\;700^{\circ}C$. The hysteresis of C-V curves and trapping charge densities were decreased after annealing process. As annealing temperature became higher from $500^{\circ}C\;to\;700^{\circ}C$, the capacitance equivalent thickness (CET) was increased from 1.66 nm to 1.76 nm and the leakage current at -1 V was decreased from $1.70{\times}10^{-4}\;to\;5.68{\times}10^{-5}\;A/cm^2$.

• Journal of the Korean institute of surface engineering
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• v.27 no.4
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• pp.234-240
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• 1994

A large area impurity doping method for poly-Si TFT LCD has been developed. The advantage of this method is the doping of impurities into Si over a large area without mass separation and beam scanning. Phosphorus diluted in hydrogen was discharged by RF(13.56MHz) power and ions from discharged gas were accelerated by DC acceleration voltage and were implanted into deposited Si films. The annealing characteristic of this method was similar to that of the ion implantation method in the low doping concentration. Three mechanisms were evolved in the annealing characteristics of phosphorus doped Si films. Point defects annihilation and the retrogradation of dopant atoms at grain boundaries as a result of grain growth played a major role at low and high annealing temperature, respectively. However, due to the dopant segregation, the reverse annealing range existed at intermediate annealing temperature.

• Transactions on Electrical and Electronic Materials
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• v.12 no.3
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• pp.127-130
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• 2011

We investigated the effects of $O_2$ annealing (i.e., temperature and time) on the characteristics of hafnium silicate ($HfSi_xO_y$) films deposited on a Si substrate by atomic layer deposition process (ALD). We found that the post deposition annealing under oxidizing ambient causes the oxidation of residual Hf metal components, resulting in the improvement of electrical characteristics (e.g., hysteresis window and leakage current are decreased). In addition, we observed the annealing temperature is more important than the annealing time for post deposition annealing. Based on these observations, we suggest that post deposition annealing under oxidizing ambient is necessary to improve the electrical characteristics of $HfSi_xO_y$ films deposited by ALD. However, the annealing temperature has to be carefully controlled to minimize the regrowth of interfacial oxide, which degrades the value of equivalent oxide thickness.

• Journal of the Korean Society for Heat Treatment
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• v.17 no.2
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• pp.78-86
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• 2004

Effects of the annealing parameters on the formation of ferrites transformed at low temperatures were studied in cold-rolled ultra low carbon steels with niobium and/or chromium. Niobium and chromium were found to be effective in the formation of the low temperature transformation ferrites. The low temperature transformation ferrites more easily formed when both higher annealing temperature and longer annealing time, allowing substitutional alloying elements to distribute between phases, are in combination with faster cooling rate. It was found from EBSD study that the additions of niobium or chromium resulted in the increase in the numbers of high angle grain boundaries and the decrease in those of the low angle grain boundaries in the microstructures. Both granular bainitic ferrite and bainitic ferrite were characterized by the not clearly etched grain boundaries in light microscopy because of the low angle grain boundaries.

• Proceedings of the KIEE Conference
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• 1992.07a
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• pp.288-289
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• 1992

The method of simulated annealing is a technique that has recently attracted significant attention as suitable for optimization problem of very large scale. If the temperature is too high, then some of the structure created by the heuristic will be destroyed and unnecessary extra work will be done. If it is too low then solution is lost, similar to the case of a quenching cooling schedule in the Simulated Annealing (SA) phase. Therefore, a crucial issue in this study is the determination of the starting temperature and cooling schedule for SA phase.

• Electrical & Electronic Materials
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• v.9 no.3
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• pp.251-258
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• 1996

Sol-Gel derived ferroelectric Pb(Z $r_{0.52}$ $Ti_{0.48}$) $O_{3}$ thin films have been fabricated on Pt/Ti/ $SiO_{2}$/Si substrate. Two kinds of fast annealing methods, F-I (six times of intermediate and final annealing) and F-II(one final annealing after six times of intermediate annealing) were used for preparation of multi-coated PZT thin films. As the annealing temperature was increased, high capacitance could be obtained, for instance, 2700.angs.-thick PZT thin film annealed at 680.deg. C had a capacitance value of approximately 20nF at 1kHz. In addition, it is found that the dielectric constant is a function of the perovskite phase fraction. In case of F-I method, PZT thin film had a remanent polarization(Pr) of 8-15.mu.C/c $m^{2}$ and a coercive field( $E_{c}$) of 35-44kV/cm according to annealing temperature, whereas PZT film fabricated by F-II method had as high as 24-25.mu.C/c $m^{2}$ and 48-59kV/cm, respectively. As a result of measuring Curie temperature, PZT thin film had a range of 460-480.deg. C by F-I method and more or less higher range of 525-530.deg. C by F-II method, which implied that different microstructures could cause the different Curie temperature. Through I-V measurement, leakage current of PZT thin film fabricated by F-I and F-II methods was 64nA/c $m^{2}$ and 2.2.mu.A/c $m^{2}$ in the electric field of 100kV/cm, respectively.y.y.y.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.290.2-290.2
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• 2016

Recently, organic thin-film transistors have been widely researched for organic light-emitting diode panels, memory devices, logic circuits for flexible display because of its virtue of mechanical flexibility, low fabrication cost, low process temperature, and large area production. In order to achieve high performance OTFTs, increase in accumulation carrier mobility is a critical factor. Post-fabrication thermal annealing process has been known as one of the methods to achieve this by improving the crystal quality of organic semiconductor materials In this paper, we researched the properties of pentacene films with X-Ray Diffraction (XRD) and Atomic Force Microscope (AFM) analyses as different annealing temperature in N2 ambient. Electrical characterization of the pentacene based thin film transistor was also conducted by transfer length method (TLM) with different annealing temperature in Al- and Ti-pentacene junctions to confirm the Fermi level pinning phenomenon. For Al- and Ti-pentacene junctions, is was found that as the surface quality of the pentacene films changed as annealing temperature increased, the hole-barrier height (h-BH) that were controlled by Fermi level pinning were effectively reduced.

• Transactions on Electrical and Electronic Materials
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• v.17 no.2
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• pp.104-108
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• 2016

To research the correlation between oxygen vacancy and the electrical characteristics of ZTO, which is made by using a target mixed ZnO:SnO₂=1:1, the ZnO, SnO₂ and ZTO were analyzed by PL, XPS, XRD patterns and electrical properties. It was compared with the electron orbital spectra of O 1s in accordance with the electrical characteristics of ZnO, SnO₂ and ZTO. The electrical characteristics of ZTO were improved by increasing the annealing temperatures, due to the high degree of crystal structures at a high temperature, and the physical properties of ZTO was similar to that of ZnO. The amorphous structure of SnO₂ was increased with increasing the temperature. The Schottky contact of oxide semiconductors was formed using the depletion region, which is increased by the electron-hole combination due to the annealing processes. ZnO showed the Ohmic contact in spite of a high annealing temperature, but SnO₂ and ZTO had Schottky contact. As such, it was confirmed that the electrical properties of ZTO are affected by the molecules of SnO₂.

• Transactions of Materials Processing
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• v.13 no.3
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• pp.205-210
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• 2004

The waveguide Bragg gratings have been fabricated by the phase-mask method. An excimer laser with maximum 600mJ output pulse energy and uniform phase masks have been used. Hydrogen loading is often used for enhancing the uv photosensitivity of the core, however, the resultant gratings show significant aging effect. In the present study, high temperature thermal annealing process has been investigated to obtain thermal gratings and process parameters are deduced.

• Journal of Welding and Joining
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• v.17 no.1
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• pp.133-144
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• 1999

To fine seam annealer capacity of through thickness seam annealing in terms of through thickness microstructure change with increased toughness and elongation leaving heat trace on it, high strength steel pipes of ERW with different thickness were tested in different seam annealing temperature measured on the outer surface of pipes. Annealing temperature and microstructure of the weld seam were changed through applied seam annealing condition. Toughness and tensile test with hardness and microstructure analysis were done on the annealed weld seam to fine its characteristics as a primary step and annealing characteristics according to different seam annealing condition. Through a study of annealed ERW weld seam characteristics and seam annealing technology, amount of electric power should apply in decreased manner to arranged inductors of annealer in the order of 1st, 2nd, 3rd, so on for proper seam annealing. For example of 15.4mm thick and 610mm outside diameter pipe, applied power for proper seam annealing is 600 -650kw at 1st inductor, 450 - 500kw at 2nd inductor, 200-250 kw at 3rd inductor of annealer during 10 - 12M/minute moving speed of pipe. Also, the penetration depth of heat trace along the thickness direction of weld during seam annealing can be estimated through the equation 17mm/kv$\times$voltage(kv) with the microstructure and hardness analysis of thick weld seam as well as study of seam annealing and comparison of cooling condition to CCT diagram of low carbon high strength steel. From this result, the difference between the technological applicability of full annealing condition based on phase diagram and full penetration of heat trace based on CCT diagram along the thickness of weld seam is discussed.