• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.695-702
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• 2015

A 1-V 1.6-GS/s 5.58-ENOB flash ADC with a high-speed time-domain comparator is proposed. The proposed time-domain comparator, which consumes low power, improves the comparison capability in high-speed operations and results in the removal of preamplifiers from the first-stage of the flash ADC. The time interpolation with two factors, implemented using the proposed time-domain comparator array and SR latch array, reduces the area and power consumption. The proposed flash ADC has been implemented using a 65-nm 1-poly 8-metal CMOS process with a 1-V supply voltage. The measured DNL and INL are 0.28 and 0.41 LSB, respectively. The SNDR is measured to be 35.37 dB at the Nyquist frequency. The FoM and chip area of the flash ADC are 0.38 pJ/c-s and $620{\times}340{\mu}m^2$, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.5
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• pp.1030-1037
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• 2009

SAW Sensor is greatly developed today and Reader Platform which uses SAW Sensor for temperature or pressure is required to use TDS method for low power and high speed processing. For to use this Platform, high speed timer is required to measure a short interval between reference signal and reflectior's signal. This paper proposes that platform receive SAW Sensor's signals and transform digital signal through comparator. Next the transformed signal is measured by Timer Platform and the measured interval is displayed with time. This paper proposes method of measurment of time with nano sec unit.