• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.317-318
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• 2012

현재의 반도체 산업에서 Hafnium oxide와 Hafnium silicates같은 high-k 물질은 CMOS gate와 DRAM capacitor dielectrics로 사용하기 위한 대표적인 물질에 속한다. MOSFET (metal oxide semiconductor field effect transistor)구조에서 gate length는 16 nm 이하로 계속 미세화가 연구 중이고, 또한 gate는 기존구조에서 Multi-gate구조로 다변화가 일어나고 있다. 이를 통해 게이트 절연막은 그 구조와 활용범위가 다양해지게 될 것이다. 동시에 leakage current와 dielectric break-down을 감소시키는 연구가 중요해지고 있다. 그러나 나노 영역에서의 기계적 특성에 대한 연구는 전무한 상태이다. 따라서 복잡한 회로 공정, 다양한 Multi-gate 구조, 신뢰도의 향상을 위해서는 유전박막 물질자체와 계면에서의 물리적, 기계적인 특징의 측정이 상당히 중요해지고 있다. 이에 본 연구는 Nano-indenter의 통해 경도(Hardness)와 탄성계수(Elastic modulus) 등의 측정을 통하여 시료 표면의 나노영역에서의 기계적 특성을 연구하고자 하였다. $HfO_2$게이트 절연막은 rf magnetron sputter를 이용해 Si (silicon) (100)기판위에 박막형태로 증착하였고, 이후 furnace에서 질소분위기로 온도(400, 450, $500^{\circ}C$)를 달리하여 20분 열처리를 하였다. 또한 Weibull distribution을 이용해 박막의 characteristic value를 계산하였으며, 실험결과 열처리 온도가 $400^{\circ}C$에서 $500^{\circ}C$로 증가함에 따라 경도와 탄성계수는 7.4 GPa에서 10.65 GPa으로 120.25 GPa에서 137.95 GPa으로 각각 증가하였다. 이는 재료적 측면으로 재료의 구조적 우수성이 증가된 것으로 판단된다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 추계학술발표대회
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• pp.48.1-48.1
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• 2009

Performance of organic field-effect transistors (OFETs) with various temperature-cured polyacrylate(PA) copolymer as a gate insulator was studied. The PA thin film, which was cured at an optimized temperature, showed high dielectric strength (>7 MV/cm), low leakage current density ($5{\times}10^{-9}\;A/cm^2$ at 1 MV/cm) and enabled negligible hysteresis in MIS capacitor and OFET. A field-effect mobility of ${\sim}0.6\;cm^2/V\;s$, on/off current ratio (Ion/Ioff) of ${\sim}10^5$ and inverse subthreshold slope (SS) as low as 1.22 V/decwere achieved. The high dielectric strength made it possible to scale down the thickness of dielectric, and low-voltage operation of -5 V was successfully realized. The chemical changes were monitored by FT-IR. The morphology and microstructure of the pentacene layer grown on PA dielectrics were also investigated and correlated with OFET device performance.

• 한국전기전자재료학회논문지
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• 제35권3호
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• pp.264-268
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• 2022

High pressure deuterium (HPD) annealing is an advancing technology for the fabrication of modern semiconductor devices. In this work, gate-enclosed FETs are fabricated on a silicon substrate as test vehicles. After a cycle for the HPD annealing, the device parameters such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), off-state current (I_OFF), and gate leakage (I_G) were measured and compared depending on the HPD. The HPD annealing can passivate the dangling bonds at Si-SiO₂ interfaces as well as eliminate the bulk trap in SiO₂. It can be concluded that adding the HPD annealing as a fabrication process is very effective in improving device reliability, performance, and variability.

• 전기전자학회논문지
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• 제22권1호
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• pp.205-208
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• 2018

본 연구에서는 상시불통형 p-AlGaN-게이트 질화갈륨(GaN) 이종접합 트랜지스터의 신뢰성 평가를 위한 가속열화 시험 조건을 수립하기 위해 게이트 전압 열화 시험을 진행하였다. 상시불통형 트랜지스터의 동작 조건을 고려하여 기존 상시도통형 쇼트키-게이트 소자평가에 사용되는 게이트 역전압 시험과 더불어 순전압 시험을 수행하여 열화특성을 분석하였다. 기존 상시도통형 소자와 달리 상시불통형 소자에서는 게이트 역전압 시험에 의한 열화는 관찰되지 않은 반면, 게이트 순전압 시험에서 심한 열화가 관찰되었다. 상시불통형 질화갈륨 전력 반도체 소자의 신뢰성 평가에 게이트 순전압 열화 시험이 포함되어야 함을 제안한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권2호
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• pp.63-68
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• 2003

The DC and RF characteristics of $In_{0.5}Ga_{0.5}P/In_{0.22}Ga_{0.78}As/GaAs$ p-HEMTs with a gate oxide layer of various thicknesses ($50{\;}{\AA},{\;}300{\;}{\AA}$) were investigated and compared with those of a Schottky-gate p-HEMT without the gate oxide layer. A prominent improvement in the breakdown voltage characteristics were observed for a p-HEMT having a gate oxide layer, which was implemented by using a liquid phase oxidation technique. The on-state breakdown voltage of the p-HEMT having the oxide layer of $50{\;}{\AA}$was ~2.3 times greater than that of a Schottky-gate p-HEMT. However, the p-HEMT having the gate oxide layer of $300{\;}{\AA}$ suffered from a poor gate-control capability due to the drain induced barrier lowering (DIBL) resulting from the thick gate oxide inspite of the lower gate leakage current and the higher on-state breakdown voltage. The results for a primitive p-HEMT having the gate oxide layer without any optimization of the structure and the process indicate the potential of p-HEMT having the gate oxide layer for high-power applications.

• 대한전자공학회논문지SD
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• 제39권5호
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• 한국정보통신학회논문지
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• 제11권9호
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• pp.1717-1723
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• 2007

본 연구에서는 PLZT(10/30/70), PLT(10), PZT(30/70) 강유전체 박막을 이용한 quasi-MFISFET (Metal-Ferroelectric-Insulator-Semiconductor FET) 소자를 제작하여 드레인 전류 특성을 조사하였다. 이로부터, quasi-MHSFET 소자의 드레인 전류 크기가 강유전체 박막의 분극 크기에 따라 직접적인 영향을 받으며 결정된다는 사실을 알 수 있었다. 또, ${\pm}5V$ 와 ${\pm}10V$의 게이트 전압변화를 주었을 때 메모리 윈도우는 각각 0.5V 와 1.3V 이었고, 강유전체 박막에 인가되는 전압에 의해 만들어지는 항전압의 변동에 따라 메모리 윈도우가 변화된다는 사실을 확인할 수 있었다. MFISFET 소자의 retention 특성을 알아보기 위 해 PLZT(10/30/70) 박막의 전기장과 시간지연에 따른 누설전류 특성을 측정하여 전류밀도 상수 $J_{ETO}$, 전기장 의존 요소 K, 시간 의존 요소 m을 구하고, 이들 파라미터를 이용하여 시간에 따른 전하밀도의 변화를 정량적으로 분석하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.278.1-278.1
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• 2014

Organic materials have been explored as the gate dielectric layers in thin film transistors (TFTs) of backplane devices for flexible display because of their inherent mechanical flexibility. However, those materials possess some disadvantages like low dielectric constant and thermal resistance, which might lead to high power consumption and instability. On the other hand, inorganic gate dielectrics show high dielectric constant despite their brittle property. In order to maintain advantages of both materials, it is essential to develop the alternative materials. In this work, we manufactured nanocomposite gate dielectrics composed of organic material and inorganic nanoparticle and integrated them into organic TFTs. For synthesis of nanocomposite gate dielectrics, polyimide (PI) was explored as the organic materials due to its superior thermal stability. Candidate nanoprticles (NPs) of halfnium oxide, titanium oxide and aluminium oxide were considered. In order to realize NP concentration dependent electrical characteristics, furthermore, we have synthesized the different types of nanocomposite gate dielectrics with varying ratio of each inorganic NPs. To analyze gate dielectric properties like the capacitance, metal-Insulator-metal (MIM) structures were prepared together with organic TFTs. The output and transfer characteristics of organic TFTs were monitored by using the semiconductor parameter analyzer (HP4145B), and capacitance and leakage current of MIM structures were measured by the LCR meter (B1500, Agilent). Effects of mechanical cyclic bending of 200,000 times and thermally heating at $400^{\circ}C$ for 1 hour were investigated to analyze mechanical and thermal stability of nanocomposite gate dielectrics. The results will be discussed in detail.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.92-92
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• 2009

본 논문에서는 strained Silicon-on-Insulator (sSOI) 기판에 제작된 triple-gate MOSFETs 의 이동도와 단채널 효과에 대하여 분석 하였다. Strained 실리콘에 제작된 소자는 전류의 방향이 <110> 밤항일 경우 전자의 이동도는 증가하나 정공의 이동도는 오히려 감소하는 문제점이 있다. 이를 극복하기 위하여 소자에서 전류의 방향이 <110>방향에서 45 도 회전된 <100> 방향으로 흐르게 제작하였다. Strain이 가해지지 않은 기판에 제작된 동일한 구조의 소자와 비교하여 sSOI 에 제작된 소자에서 전자의 이동도는 약 40% 정공의 이동도는 약 50% 증가하였다. 채널 길이가 100 nm 내외로 감소함에 따라 나타나는 drain induced barrier lowering (DIBL) 현상, subthreshold slope (SS)의 증가 현상에서 sSOI에 제작된 소자가 상대적으로 우수한 특성을 보였으며 off-current leakage ($I_{off}$) 특성도 sSOI기판이 더 우수한 특성을 보였다.