• International Journal of Automotive Technology
• /
• v.4 no.2
• /
• pp.57-64
• /
• 2003

The Intelligent Power Unit (IPU) utilized in Honda's Civic Hybrid Integrated Motor Assist (IMA) system was developed with the aim of making every component lighter, more compact and more efficient than those in the former model. To reduce energy loss, inverter efficiency was increased by fine patterning of the Insulated Gate Bipolar Transistor (IGBT) chips, 12V DC-DC converter efficiency was increased by utilizing soft-switching, and the internal resistance of the IMA battery was lowered by modifying the electrodes and the current collecting structure. These improvements reduced the amount of heat generated by the unit components and made it possible to combine the previously separated Power Control Unit (PCU) and battery cooling systems into a single system. Consolidation of these two cooling circuits into one has reduced the volume of the newly developed IPU by 42% compared to the former model.

• Proceedings of the Korean Society of Agricultural Engineers Conference
• /
• 2005.10a
• /
• pp.193-198
• /
• 2005

The solar energy floodgate which discusses will minimize a quotient bringing up for discussion friction resistance and it will do to write a disturbance power, with the base which will reach it will be able to use the solar power unit in order. It is a plan which to magnification supply the practicality and will give proof will the effort with the irrigation facility of the farming village. Magnification supply of the solar energy floodgate which it sees hazard the stack supervisor and the possibility the use against the farmer and the easy frost does the monitoring against and the work which it complements is necessary.

• Proceedings of the Korea Society for Industrial Systems Conference
• /
• 1997.11a
• /
• pp.451-462
• /
• 1997

A 2-dimensional numerical analysis is presented for thermal-electron heat conduction effects upon the electron transport and the drain current-voltage characteristics of submicron GaAs MESFETs, based on the use of a nonstationary hydrodynamic transport model. It is shown that for submicron GaAs MESFETs, electron heat conduction effects are significant on their internal electronic properties and also drain current-voltage characteristics. Due to electron heat conduction effects, the electron energy is greatly one-djmensionalized over the entire device region. Also, the drain current decreases continuously with increasing thermal conductivity in the saturation region of large drain voltages above 1 V. However, the opposite trend is observed in the linear region of small drain voltages below 1 V. Accordingly, for a large thermal conductivity, negative differential resistance drain current characteristics are observed with a pronounced peak of current at the drain voltage of 1 V. On the contrary, for zero thermal conductivity, a Gunn oscillation characteristic is observed at drain voltages above 2 V under a zero gate bias condition.

• Proceedings of the Korea Society for Industrial Systems Conference
• /
• 2002.11a
• /
• pp.363-370
• /
• 2002

A substrate network model characterizing substrate effect of submicron MOS transistors for RF operation and its parameter extraction with physically meaningful values are presented. The proposed substrate network model includes a single resistance and inductance originated from ring-type substrate contacts around active devices. Model parameters are extracted from S-parameter data measured from common-bulk configured MOS transistors with floating gate and use where needed with out any optimization. The proposed modeling technique has been applied to various-sized MOS transistors. Excellent agreement the measurement data and the simulation results using extracted substrate network model up to 30㎓

• Proceedings of the KIEE Conference
• /
• 1988.07a
• /
• pp.387-390
• /
• 1988

The increases in the packing density and the resulting shrinkage of silicon integrated circuit dimensions led to the investigation and successful of the deposited silicide layers as the gate and interconnection and contact metallization. In this paper evaporated Co films on n-Si have been rapid thermal annealed in $N_2$ambient at temperature of $400^{\circ}C-1000^{\circ}C$. The Co silicide formation is characterized by sheet resistance (4PP). Also, silicide growth rate and its reproductivity has been examined by SEM.

• Journal of the Semiconductor & Display Technology
• /
• v.19 no.3
• /
• pp.82-87
• /
• 2020

The comprehensive and physics-based compact noise models for advanced CMOS devices were presented. The models incorporate important physical effects in nanoscale MOSFETs, such as the low frequency correlation effect between the drain and the gate, the trap-related phenomena, and QM (quantum mechanical) effects in the inversion layer. The drain current noise model was improved by including the tunneling assisted-thermally activated process, the realistic trap distribution, the parasitic resistance, and mobility degradation. The expression of correlation coefficient was analytically described, enabling the overall noise performance to be evaluated. With the consideration of QM effects, the comprehensive low frequency noise performance was simulated over the entire bias range.

• Journal of the Korean Ceramic Society
• /
• v.31 no.1
• /
• pp.74-78
• /
• 1994

Degradation of thin oxide by doped poly-Si and its improvement were studied. The gate oxide can be degraded by phosphorous in poly-Si doped POCl3. The degradation is increased with the decrement of sheet resistance and poly-Si thickness. Oxide failures of amorphous-Si are higher than those of poly-Si. In-situ double deposition of amorphous-Si, 54$0^{\circ}C$/30 nm, and poly-Si, 6$25^{\circ}C$/220 nm, forms the mismatch structure of grain boundary between amorphous-Si and poly-Si, and suppresses the excess phosphorous on oxide surface by the mismatch structure. The control of phosphorous through grain boundary improves the oxide reliability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1998.06a
• /
• pp.71-74
• /
• 1998

In this Paper, we investigate the electrical properties of ultra-thin(70${\AA}$) nitrided(NO) and reoxidized nitrided oxide(ONO) film that ale considered to be premising candidates for replacing conventional silicon dioxide film in ULSI level integration. we studied I$\sub$g/-V$\sub$g/ characteristics to know the effect of nitridation and reoxidation on the current conduction, leakage current time-dependent dielectric breakdown(TDDB) to evaluate charge-to-breakdown(Q$\sub$bd/), and the effect of stress temperature(25, 50, 75, 100$^{\circ}C$) and compared to those with thermal gate oxide(SiO$_2$) of identical thickness. From the measurement results, we find that reoxidized nitrided oxide(ONO) film shows superior dielectric characteristics, leakage current, and breakdown-to-charge(Qbd) performance over the NO film, while maintaining a similar electric field dependence compared to NO layer. Besides, ONO film has strong resistance against variation in temperature.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.1
• /
• pp.220-225
• /
• 2018

A class E power oscillator is demonstrated for 6.78-MHz wireless power transfer system. The oscillator is designed with a class E power amplifier to use an LC feedback network with a high-Q inductor between the input and the output. Multiple capacitors are used to minimize the variation of the oscillation frequency by capacitance tolerance. The gate and drain bias voltages with opposite characteristics to make the frequency shift of the oscillator are connected in a resistance distribution circuit located at the output of the low drop-out regulator and supplied bias voltages for class E operation. The measured output of the class E power oscillator, realized using the co-simulation, shows 9.2 W transmitted power, 6.98 MHz frequency and 86.5% transmission efficiency at the condition with 20 V $V_{DS}$ and 2.4 V $V_{GS}$.

• Proceedings of the KIEE Conference
• /
• 2003.07c
• /
• pp.1955-1957
• /
• 2003

This paper presents a novel defected ground structure (DGS) and its application to a microwave oscillator. The presented oscillator is designed so as to use the suggested defected ground structure as a feedback loop inducing a negative resistance as well as a frequency-selective circuit. Applying the feedback loop between the drain and the gate of a FET device produces precise phase conversion in the feedback loop. The equivalent circuit parameters of the DGS are extracted by using a three-dimensional EM calculations and simple circuit analysis method. The implemented 1.07 GHz oscillator exhibits 0 dBm output power with over 15% dc-to-RF power efficiency and -106 dBc/Hz phase noise at 100 kHz offset from carrier.