• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
• /
• 2005.05a
• /
• pp.322-325
• /
• 2005

The separation mechanism is installed to separate a note one by one from the stacked notes and the overlap type, one of separation mechanism, has been used a lot in financial equipments like ATM. This paper has compared and estimated analysis results using finite element method with experimental results over various parameters such as conditions of note, overlap value, roller shapes, which affect the friction force (resistance) exerting on notes between rollers. Consequently, the effect of various parameters on the performance of overlap type separation mechanism can be known and optimal shape and overlap value can be obtained.

• Journal of the Korean Ceramic Society
• /
• v.35 no.3
• /
• pp.259-263
• /
• 1998

WSi2/CVD-Si/SiO2/Si-substrate의 폴리사이드 구조에서 실리콘 증착 POCl3 확산 그리고 WSi2 증착 유무에 따른 Thin oxide 특성을 연구했다 WSi2 막을 증착하지 않은 CVD-Si/SiO2/Si-substrate 구조에서 CVD-Si을 po-lycrystalline-Si으로 증착한 시편이 amorphous-Si을 증착한 시편보다 산화막 불량이 적다 WSi2 를 증착시킨 WSi2/CVD-Si/SiO2./Si-substrate의 구조에서 CVD-Si의 polycrystalline-Si 혹든 amorphous-Si 의 막 증착에 따른 thin oxide의 불량율 차이는 미미하다 산화막 불량은 CVD-Si에 확산시킨 인(P) 증가 즉 면저항(sheet resistance) 감소로 증가한다. Thin oxide의 절연특성은 WSi2 증착으로 저하된다 WSi2 증착으로 산화막 두께는 증가하나 막 특성은 열등해져 산화막 절연성이 떨어진다.

• Proceedings of the KIEE Conference
• /
• 1989.07a
• /
• pp.377-379
• /
• 1989

Very thin gate oxide(100-300A) MOS capacitor has been fabricated. The effect of series resistance must be calculated and the exact metal-semiconductor work function difference should be obtained to get the fixed oxide charge density exisiting in oxide. Dilute oxidation make sagy to control oxide thickness and reduce fixed oxide charge density. In case of dilute oxidation, fixed oxide charge density depends on oxidation time. If oxide is very thin, the annealing effect is ignored.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.563-564
• /
• 2008

This paper presents a new Insulated Gate Bipolar Transistor(IGBT) for power switching device based on Non Punch Through(NPT) IGBT structure. The proposed structure has adding N+ beside the P-base region of the conventional IGBT structure. The proposed device has faster turn-off time and lower forward conduction loss than the conventional IGBT structure.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.759-762
• /
• 2002

In this paper, a voltage-controlled linear variable resistor (VCLVR) using a floating-gate MOS-FET (FG-MOSFET) is proposed. The proposed-circuit is the grounded VCLVR consists of only an ordinary MOSFET and an FG-MOSFET. The advantage of the proposed VCLVR are low-voltage and wide-input range. Next, as applications, a floating-node voltage controlled variable resistor and an operational transconductance amplifier using the proposed VCLVRs are proposed. The performance of the proposed circuits are characterized through HSPICE simulations with a standard 0.6 ${\mu}$m CMOS process. simulations of the proposed VCLVR demonstrate a resistance value of 40 k$\Omega$ to 338 k$\Omega$ and a THD of less than 1.1 %.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.815-818
• /
• 2003

New sensing and writing schemes for a magneto-resistive random access memory (MRAM) with a twin cell structure are proposed. In order to enhance the cell reliability, a scheme of the low voltage precharge is employed to keep the magneto resistance (MR) ratio constant. Moreover, a common gate amplifier is utilized to provide sufficient voltage signal to the bit line sense amplifiers under the small MR ratio structures. To enhance the writing reliability, a current mode technique with tri-state current drivers is adopted. During write operations, the bit and /bit lines are connected. And 'HIGH' or 'LOW' data is determined in terms of the current direction flowing through the MTJ cell. With the viewpoint of the improved reliability of the cell behavior and sensing margin, HSPICE simulations proved the validity of the proposed schemes.

• ETRI Journal
• /
• v.20 no.1
• /
• pp.37-45
• /
• 1998

Reduced surface field lateral double-diffused MOS transistor for the driving circuits of plasma display panel and field emission display in the 120V region have been integrated for the first time into a low-voltage $1.2{\mu}m$ analog CMOS process using p-type bulk silicon. This method of integration provides an excellent way of achieving both high power and low voltage functions on the same chip; it reduces the number of mask layers double-diffused MOS transistor with a drift length of $6.0{\mu}m$ and a breakdown voltage greater than 150V was self-isolated to the low voltage CMOS ICs. The measured specific on-resistance of the lateral double-diffused MOS in $4.8m{\Omega}{\cdot}cm^2$ at a gate voltage of 5V.

• Proceedings of the Korea Society of Information Technology Applications Conference
• /
• 2002.11a
• /
• pp.363-370
• /
• 2002

A substrate network model characterizing substrate effect of submicron MOS transistors for RF operation and its parameter extraction with physically meaningful values are presented. The proposed substrate network model includes a single resistance and inductance originated from ring-type substrate contacts around active devices. Model parameters are extracted from S-parameter data measured from common-bulk configured MOS transistors with floating gate and use where needed with out any optimization. The proposed modeling technique has been applied to various-sized MOS transistors. Excellent agreement the measurement data and the simulation results using extracted substrate network model up to 30GHz.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.9
• /
• pp.1375-1380
• /
• 1989

Mobility reduction parameters are extracted using a method based on the exploitatiion of Id-Vg and Gm-Vg characteristics of short channel n-MOSFETs in strong inversion region at room temperature. It is found that the reduction of the maximum field effect mobility, \ulcornerFE,max, with the channel length is due to i) the difference between the threshold voltage and the gate voltage which corresponds to the maximum transconductance, and ii) the channel length dependence of the mobility attenuation coefficient, \ulcorner The low field mobility, \ulcorner, is found to be independent of the channel length down to 0.25 \ulcorner ofeffective channel length. Also, the channel length reduction, -I, the mobility attenuation coefficient, \ulcorner the threshold voltage, Vt, and the source-drain resistance, Rsd, are determined from the Id-Vg and -gm-Vg characteristics n-MOSFETs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.28 no.8
• /
• pp.496-500
• /
• 2015

This paper was proposed the theoretical research and optimal design 3000V super junction NPT IGBT for using electrical automotive and power conversion. Because super junction IGBT was showed ultra low on resistance, it was structure that can improve the thermal characteristics of conventional NPT IGBT. The electrical characteristics of super junction NPT IGBT were 2.52 V of on state voltage drop, 4.33 V of threshold voltage and 2,846 V breakdown voltage. We did not obtaing 3,000 V breakdown voltage but we will obtain 3,000 V breakdown voltage through improving p pillar layer. If we are carried this research, This device will be used electrical automotive, power conversiton and high speed train.