• ETRI Journal
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• 제44권5호
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• pp.849-858
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• 2022

Dynamic voltage frequency scaling (DVFS) has been widely adopted for runtime power management of various processing units. In the case of neural processing units (NPUs), power management of neural network applications is required to adjust the frequency and voltage every layer to consider the power behavior and performance of each layer. Unfortunately, DVFS is inappropriate for layer-wise run-time power management of NPUs due to the long latency of voltage scaling compared with each layer execution time. Because the frequency scaling is fast enough to keep up with each layer, we propose a layerwise dynamic frequency scaling (DFS) technique for an NPU. Our proposed DFS exploits the highest frequency under the power limit of an NPU for each layer. To determine the highest allowable frequency, we build a power model to predict the power consumption of an NPU based on a real measurement on the fabricated NPU. Our evaluation results show that our proposed DFS improves frame per second (FPS) by 33% and saves energy by 14% on average, compared with DVFS.

• 정보과학회 컴퓨팅의 실제 논문지
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• 제20권9호
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• pp.483-491
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• 2014

현대의 컴퓨터 시스템에서는 동적 전압/주파수 조정(DVFS: Dynamic Voltage/Frequency Scaling) 기법을 이용하여 성능과 전력 소모의 균형을 이루도록 한다. DVFS 정책의 유용성은 높아진 주파수에 따른 소모 전력에 대한 성능 향상 정도에 달려있다. 특히 메모리 I/O가 많은 응용의 경우 CPU 주파수 상승에 비례하여 성능이 향상되지 않는 경우가 많다. 본 논문에서는 메모리 접근 빈도에 기반하여 CPU 주파수 조정의 상한을 결정하도록 하였다. 명령어 당 메모리 접근(최종 수준 캐시 미스) 빈도에 따라 CPU 주파수 상향으로 인한 성능 향상이 제한되는 것을 실험으로 확인하고, 성능 향상의 이득이 작아지는 CPU 주파수를 제시하도록 한다. 본 논문의 기법을 적용한 실험 결과는 메모리 접근 빈도가 높은 응용에 대하여 30% 이상의 에너지 효율 상승이 있음을 보인다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.282-285
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• 2002

In this paper, we designed of low power system by using dynamic scaling. As an effective low-power design, dynamic voltage/frequency scaling recently has received a lot of attention. In dynamic frequency scheme, all execution cycles are driven by the clock frequency that switched frequency dynamically at run time. The algorithm schedules lower frequency operators at earlier steps and higher frequency operators to later steps. This algorithm assigned the frequency for each execution cycle then it adjusted the voltage associated with the frequency.

• 디지털콘텐츠학회 논문지
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• 제10권2호
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• pp.217-223
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• 2009

XScale PXA255 기반 Embedded Linux 환경에서 전력 소비를 줄이기 위해 DFS(Dynamic Frequency Scaling) 기법의 디바이스 드라이버를 제작하고 이 디바이스 드라이버가 포팅되어 있는 임베디드 타겟보드의 전력을 관리하기 위한 미들웨어 DFM(Dynamic Frequency Management)를 설계하고 구현하여 임베디드 시스템의 전력 소비를 감소하는 방법을 제시한다.

• 융합신호처리학회논문지
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• 제9권2호
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• pp.98-103
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• 2008

기존의 대표적인 디지털 통신방식으로 주파수 편이 변조(FSK: frequency shift keying), 위상 편이 변조(PSK: phase shift keying), 진폭 편이 변조(ASK: amplitude shift keying) 방식들이 있다. 본 논문에서는 디지털 통신에서 스케일링 함수(scaling function)와 웨이브릿(wavelet)을 이용한 새로운 웨이브릿 편이 변조(wavelet shift keying) 시스템을 제안한다. 웨이브릿 변환은 저주파 계수와 고주파 계수로 구성된다. 입력이 1인 신호에 대하여 임펄스 응답을 구하면, 스케일링 함수와 웨이브릿 함수로 나누어진다. 스케일링 함수를 1로, 웨이브릿 함수를 0으로 할당하여 2진 데이터를 변조한다. 모의실험 결과 제안한 알고리즘이 잡음에 강인함을 확인하였다.

• 한국치위생학회지
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• 제15권6호
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• pp.1107-1116
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• 2015

Objectives: The purpose of this study was to examine awareness and satisfaction toward health insurance coverage of scaling. Methods: A self-reported questionnaire was completed by 221 patients receiving scaling service from July to August, 2014. The informed consent was approved after the explanation of purpose of the study. The questionnaire consisted of general characteristics of the subjects, awareness toward health insurance coverage of scaling, scaling service covered by health insurance, and satisfaction with health insurance service. Results: Those recognizing the health insurance service extension accounted for 87.3 percent and 67.4 percent answered that the appropriate coverage age would be 20 years old. The recommendable frequency of scaling was once a year and this accounted for 49.3 percent. Fifty percent of the subjects thought health insurance coverage of scaling would be reasonable and 34.8 percent acquired the information from mass media. The most common service providers were dental hygienists and the length of service was from 20 to 30 minutes. The contents of service included scaling service, toothbrushing method, and oral care. The satisfaction was 4.39 points. Conclusions: The health insurance coverage of scaling will improve the oral health and quality of life in Korean adults. So the government should try to extend the scaling coverage by health insurance and the frequency of scaling.

• Korea-Australia Rheology Journal
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• 제19권3호
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• pp.141-146
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• 2007

We examine the wall contact of a $3\;{\mu}m$ tethered DNA chain's free end under shear with a focus on developing schemes for double-tethering in the application of making scaffolds for molecular wires. At this scale our results are found to be highly dependent on small length scale rigidity. Chain-end-wall contact frequency, mean fractional extension deficit upon contact, and standard deviation in extension upon contact are examined for scaling with dimensionless flow strength, Wi. Predictions made using a one dimensional approximation to the Smoluchowski equation for a dumbbell and three dimensional dumbbell simulations produce extension deficit, standard deviation, and frequency scaling exponents of -1/3, -1/3, and 2/3, respectively whereas more fine-grained Kratky-Porod (KP) simulations produce scaling exponents of -0.48, -0.42, and 0.76. The contact frequency scaling of 2/3 is derived from the known results regarding cyclic dynamics Analytical scaling predictions are in agreement with those previously proposed for ${\lambda}-DNA$. [Ladoux and Doyle, 2000, Doyle et al., 2000]. Our results suggest that the differences between the dumbbell and the KP model are associated with the addition of chain discretization and the correct bending potential in the latter. These scaling results will aide future exploration in double tethering of DNA to a surface.

• Earthquakes and Structures
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• 제5권2호
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• pp.129-142
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• 2013

Linear and nonlinear time history analyses have been becoming more common in seismic analysis and design of structures with advances in computer technology and earthquake engineering. One of the most important issues for such analyses is the selection of appropriate acceleration time histories and matching these histories to a code design acceleration spectrum. In literature, there are three sources of acceleration time histories: artificial records, synthetic records obtained from seismological models and accelerograms recorded in real earthquakes. Because of the increase of the number of strong ground motion database, using and scaling real earthquake records for seismic analysis has been becoming one of the most popular research issues in earthquake engineering. In general, two methods are used for scaling actual earthquake records: scaling in time domain and frequency domain. The objective of this study is twofold: the first is to discuss and summarize basic methodologies and criteria for selecting and scaling ground motion time histories. The second is to analyze scaling results of time domain method according to ASCE 7-05 and Eurocode 8 (1998-1:2004) criteria. Differences between time domain method and frequency domain method are mentioned briefly. The time domain scaling procedure is utilized to scale the available real records obtained from near fault motions and far fault motions to match the proposed elastic design acceleration spectrum given in the Eurocode 8. Why the time domain method is preferred in this study is stated. The best fitted ground motion time histories are selected and these histories are analyzed according to Eurocode 8 (1998-1:2004) and ASCE 7-05 criteria. Also, characteristics of both near fault ground motions and far fault ground motions are presented by the help of figures. Hence, we can compare the effects of near fault ground motions on structures with far fault ground motions' effects.

• 한국지구과학회지
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• 제37권5호
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• pp.277-285
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• 2016

We introduce a depth scaling strategy to improve the accuracy of frequency-domain elastic full waveform inversion (FWI) using the new pseudo-Hessian matrix for seismic data without low-frequency components. The depth scaling strategy is based on the fact that the damping factor in the Levenberg-Marquardt method controls the energy concentration in the gradient. In other words, a large damping factor makes the Levenberg-Marquardt method similar to the steepest-descent method, by which shallow structures are mainly recovered. With a small damping factor, the Levenberg-Marquardt method becomes similar to the Gauss-Newton methods by which we can resolve deep structures as well as shallow structures. In our depth scaling strategy, a large damping factor is used in the early stage and then decreases automatically with the trend of error as the iteration goes on. With the depth scaling strategy, we can gradually move the parameter-searching region from shallow to deep parts. This flexible damping factor plays a role in retarding the model parameter update for shallow parts and mainly inverting deeper parts in the later stage of inversion. By doing so, we can improve deep parts in inversion results. The depth scaling strategy is applied to synthetic data without lowfrequency components for a modified version of the SEG/EAGE overthrust model. Numerical examples show that the flexible damping factor yields better results than the constant damping factor when reliable low-frequency components are missing.

• Journal of Information Processing Systems
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• 제7권1호
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• pp.93-102
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• 2011

In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel post-silicon tuning methodology to scale optimum voltage and frequency "dynamically". The proposed design technique will use our PVT sensor circuits to monitor the variations and based on the monitored variation data, voltage and frequency will be compensated "automatically". During the compensation process, supply voltage is dynamically adjusted to guarantee the minimum total power consumption without violating the frequency requirement. The simulation results show that the proposed technique can reduce the total power by 85% and the static power by 53% on average for the selected ISCAS'85 benchmark circuits with 45 nm CMOS technology compared to the results of the traditional PVT compensation method.