• Journal of KIISE:Computing Practices and Letters
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• v.9 no.1
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• pp.13-24
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• 2003

MPEG-4 is a standard for multimedia applications and provides a set of technologies to satisfy the needs of authors, service providers and end users alike. In this paper, we suggest a Real-time Multiple Circular Buffer (M4RM Buffer) model, which is suitable for streaming these MPEG-4 contents efficiently. M4RM buffer generates each structure of the buffer, which matches well with each object composing an MPEG-4 content, according to the transferred information, and manipulates multiple read/write operations only by its reference. It divides the decoder buffer and the composition buffer, which are described in the standard, by the unit of frame allocated to minimize the range of access. This buffer unit of a frame is allocated according to the object description. Also, it processes the objects synchronization within the buffer and provides APIs for an efficient buffer management to process the real-time user events. Based on the performance evaluation, we show that M4RM buffer model decreases the waiting time in a buffer frame, and so allows the real-time streaming of an MPEG-4 content using the smaller size of the memory block than IM1-2D and Window Media Player.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.43-53
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• 2010

Wide deployment of high resolution video services leads to active studies on high speed video processing. Especially, prevalent employment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. In this paper, we propose a novel parallel H.264/AVC decoding scheme on a multi-core platform. Parallel H.264/AVC decoding is challenging not only because parallelization may incur significant synchronization overhead but also because software may have complicated dependencies. To overcome such issues, we propose a novel approach called Multi-Threaded Parallelization(MTP). In MTP, to reduce synchronization overhead, a separate thread is allocated to each stage in the pipeline. In addition, an efficient memory reuse technique is used to reduce the memory requirement. To verify the effectiveness of the proposed approach, we parallelized FFmpeg H.264/AVC decoder with the proposed technique using OpenMP, and carried out experiments on an Intel Quad-Core platform. The proposed design performs better than FFmpeg H.264/AVC decoder before the parallelization by 53%. We also reduced the amount of memory usage by 65% and 81% for a high-definition(HD) and a full high-definition(FHD) video, respectively compared with that of popular existing method called 2Dwave.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.3 s.345
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• pp.84-94
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• 2006

In this paper, we propose the algorithm to reduce guard time of UWB MAC time slot for throughput gain. In the proposed draft by multiband ofdm alliance (MBOA), Guard time of each medium access slot (MAS) is composed of shortest inter-frame space (SIFS) and MaxDrift which is the time caused by maximum frequency offset among devices. In this paper, to reduceguard time means that we nearly eliminate MaxDrift term from guard time. Each device of a piconet computes relative frequency offset from the device initiating piconet using periodically consecutive transferred beacon frames. Each device add or subtract the calculated relative frequency offset to the estimated each MAS starting point in order to synchronize with calculated MAS starting point of the device initiating piconet. According to verification of simulations, if the frequency offset estimator is implemented with 8 decimal bit, the ratio of the wasted time to Superframe is always less than 0.0001.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.641-648
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• 2011

Frequency domain equalization is the most promising technology that has relatively low complexity in multipath channel. A frame of single carrier system with frequency domain equalization (SC-FDE) has cyclic prefix to mitigate effect of delay spread. After synchronization and equalization procedure on the SC-FDE system, common phase offset (CPO) that can introduce performance degradation caused by phase mismatch between transmitter and receiver oscillators is remained. In this paper, common phase offset tracking in frequency domain is proposed. To track CPO, constant amplitude zero autocorrelation code sequence as training sequence is adopted. By using numerical results, performance of mean square error is evaluated. The results show that MSE of CPO has similar performance compare to the time-domain estimation and there is no need of domain conversion.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.4
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• pp.150-157
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• 2008

This paper presents a design and implementation of realtime video player that operates on a tiled-display system consisting of multiple PCs to provide a very large and high resolution display. In the proposed system, the master process transmits a compressed video stream to multiple PCs using UDP multicast. All slaves(PC) receive the same video stream, decompress, clip their designated areas from the decompressed video frame, and display it to their displays while being synchronized with each other. A simple synchronization mechanism based on the H/W clock of each slave is proposed to avoid the skew between the tiles of the display, and a flow-control mechanism based on the bit-rate of the video stream and a pre-buffering scheme are proposed to prevent the jitter The proposed system is implemented with Microsoft DirectX filter technology in order to decouple the video/audio codec from the player.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.754-757
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• 2007

In this paper, we present an implementation and it's real-sea test of an underwater acoustic data communication system, which allows the system to reduce complexity and increase robustness in time variant underwater environments. For easy adaptation to complicated and time-varying environments of the ocean, all-digital transmitter and receiver systems were implemented. For frame synchronization the CAZAC sequence was used, and QPSK modulation/ demodulation method with carrier frequency of 25kHz and a bandwidth of 5kHz were applied to generate 10kbps transmission rate including overhead. To improve transmission quality, we used several techniques and algorithms such as adaptive beamforming, adaptive equalizer, and convolution coding/Viterbi decoding. for the verification of the system performance, measurement of BER has been done in a very shallow water with depth of 8m at JangMok, Geoje. During the experiment, image data were successfully transmitted up to about 7.4km.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2B
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• pp.125-136
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• 2002

It is very important to acquire the synchronization in a intercell asynchronous WCDMA system, and it is carried out through the three-step cell search process. The cell search can operate in a stepwise parallel manner, where each step works in pipelined operation, to reduce the cell search time. In case that the execution time is set to be the same in each step, excessive accumulations will be caused in both step 1 and step 3, because step 2 should take at least one frame for its processing. In general, the effect of post-detection integration becomes saturated as the number of the accumulations increases. Therefore, the stepwise parallel scheme does not give much enhancement. In this paper, the performance of the stepwise parallel processing for cell search in WCDMA system is analyzed over Rayleigh fading channels. Through the analysis, the effect of cell search parameters such as the number of accumulations in each step and the power ratio allocated among channels is investigated. In addition, the performance of the stepwise parallel cell search is improved by adjusting the execution time appropriately for each step and is compared with that of the conventional stepwise serial processing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1B
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• pp.24-33
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• 2002

The cell search scheme for W-CDMA consists of the following three stages: slot synchronization(1st stage), group identification and frame boundary detection(2nd stage), and long code identification(3rd stage). The performance of the cell search when a mobile station is switched on, which is referred to as initial cell search, is decreased by the initial frequency and timing error. In this paper, we propose the pipeline structured initial cell search scheme using time trackers to compensate for the impact of the initial timing error in the stage 2 and stage 3. The simulation results show that the performance of the proposed scheme is maximal 1.5dB better than that of the conventional one when the initial timing error is near ${\pm}T_c$/2.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.121-126
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• 2006

This paper report on the design and implementation of a 9.6kbps DSSS CDMA modem for a medium speed wireless link. The proposed modem provides a general purpose I/O interface with a microprocessor. The I/O interface consists of 8-bit data bus, chip enable, read/write, and interrupt pins. In transmit block, the 8-bit data delivered from the I/O interface buffer is converted to 9.6kbps serial data, which are spreaded into 76.8kcps with 8-bit PN code generated inside the modem by direct sequence method. An 8-bit training sequence is preceded in the data frame for data synchronization in receiver. In receiver block the PN code is synchronized from the received data spreaded to 76.8kcps and find the data timing from the 8-bit training sequence. We have used the Early-and-Late integration method. The modem has been implemented and verified using a Xilix FPGA board and has been fabricated as an ASIC CHIP through Hynir $0.25{\mu}m$ CMOS. The multiple accessing method is DSSS CDMA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1727-1734
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• 2011

In this paper, a position control scheme of the ink droplet is presented for the high image quality and print speed ink jet printer. The proposed scheme estimates the impact position and compensates it by control of the jet strobe time based on the dynamic equations describing the moving trajectory of the ejected ink droplet. Compared to the conventional jet strobe control which is based on the simple synchronization with the position signal of the ink jet nozzle, the proposed control scheme provides more accurate impact position control while the carrier is moving with accelerated or decelerated speed as well as steady state speed with fluctuations. The availability of printing during the acceleration and deceleration states of the carrier moving enables the print speed up and the frame size down which means the cost down.