• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.5
• /
• pp.554-562
• /
• 2015

This paper presents the design and analysis of gate-recessed AlGaN/GaN Fin-type Field-Effect Transistor (FinFET). The three-dimensional (3-D) technology computer-aided design (TCAD) simulations were performed to analyze the direct-current (DC) and radio-frequency (RF) characteristics for AlGaN/GaN FinFETs. The fin width ($W_{fin}$) and the height of GaN layer ($H_{GaN}$) are the design parameters used to improve the electrical performances of gate-recessed AlGaN/GaN FinFET.

• Journal of the Korean Society of Industry Convergence
• /
• v.22 no.4
• /
• pp.405-413
• /
• 2019

In this study, a progressive process was performed to fabricate the inner fin of a high-efficiency heat exchanger. A forming simulation was also carried out on the concavo-convex of the inner fin, forming a simulation based on elastic-plastic finite element method. The forming analysis where the speed of the press descended and ascended was set to five seconds showed that the effective stress was at a maximum of about 69 MPa in the curved portion where the bending occurred. Therefore, the die was designed based on the simulation results, and the inner fin die was installed on the 400-ton capacity press. After that, the inner fin fabrication experiment was conducted under the same condition as the simulation. Crack was not found from the curved portion of the concavo-convex of the inner fin. The profile of the concavo-convex of the prepared inner fin measured 6.7~6.8 mm in depth, 2.65~2.7 mm in width, and 0.3 mm in thickness.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.2
• /
• pp.134-142
• /
• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.4
• /
• pp.302-310
• /
• 2008

This paper puts forward an advanced consideration on the design of scaled multiple-gate FET (MuGFET); the aspect ratio ($R_{h/w}$) of the fin height (h) to fin width (w) of MuGFET is considered with the aid of 3-D device simulations. Since any change in the aspect ratio must consider the trade-off between drivability and short-channel effects, it is shown that optimization of the aspect ratio is essential in designing MuGFET's. It is clearly seen that the triple-gate (TG) FET is superior to the conventional FinFET from the viewpoints of drivability and short-channel effects as was to be expected. It can be concluded that the guideline of w < L/3, where L is the channel length, is essential to suppress the short-channel effects of TG-FET.

• Nuclear Engineering and Technology
• /
• v.55 no.1
• /
• pp.364-372
• /
• 2023

The space reactor is the primary energy supply for future space vehicles and space stations. The radiator is one of the essential parts of a space reactor. Therefore, the research on radiators can improve the heat dissipation power, reduce the quality of radiators, and make the space reactor smaller. Based on MOOSE multi-physics numerical calculation platform, a simulation program for the combination of heat pipe and fin at the end of heat pipe radiator is developed. It is verified that the calculation result of this program is accurate and the calculation speed is fast. Analyze the heat transfer characteristics of the combination with heat pipe and fin, and obtain its internal temperature field. Based on the calculation results, the influence of structural parameters on the heat dissipation power is analyzed. The results show that when the fin width is 0.25 m, fin thickness is 0.002 m, condensing section length is 0.5425 m and heat pipe radius is 0.014 m, the power-mass ratio is the highest. When the temperature is 700K-900K, the heat dissipation power increases 41.12% for every 100K increase in the operating temperature. Smaller fin width and thinner fin thickness can improve the power-mass ratio and reduce the radiator quality.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.1
• /
• pp.51-55
• /
• 2007

This paper investigates the subthreshold behavior of Fin Field Effect Transistor (FinFET). The FinFET is considered to be an alternate MOSFET structure for the deep sub-micron regime, having excellent device characteristics. As the channel length decreases, the study of subthreshold behavior of the device becomes critically important for successful design and implementation of digital circuits. An accurate analysis of subthreshold behavior of FinFET was done by simulating the device in a 3D process and device simulator, Taurus. The subthreshold behavior of FinFET, was measured using a parameter called S-factor which was obtained from the $In(I_{DS})\;-\;V_{GS}$ characteristics. The value of S-factor of devices of various fin dimensions with channel length $L_g$ in the range of 20 nm - 50 nm and with the fin width $T_{fin}$ in the range of 10 nm - 40 nm was calculated. It was observed that for devices with longer channel lengths, the value of S-factor was close to the ideal value of 60 m V/dec. The S-factor increases exponentially for channel lengths, $L_g\;<\;1.5\;T_{fin}$. Further, for a constant $L_g$, the S factor was observed to increase with $T_{fin}$. An empirical relationship between S, $L_g$ and $T_{fin}$ was developed based on the simulation results, which could be used as a rule of thumb for determining the S-factor of devices.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.7
• /
• pp.1-7
• /
• 2010

The device performances of accumulation-mode Pi-gate pMOSFETs with different fin widths have been characterized at high operating temperatures. The device fin height is 10nm and fin widths are 30nm, 40nm, and 50nm. The variation of the drain current, threshold voltage, subthreshold swing, effective mobility, and leakage current have been investigated as a function of operating temperatures. The drain current at high temperature is slightly larger than at room temperature. The variation of the threshold voltage as a function of the operating temperature is smaller than that of the inversion-mode MOSFETs. The effective mobility is decreased with the increase of operating temperature. It is observed that the effective mobility is enhanced as the fin width decreases.

• Journal of Sensor Science and Technology
• /
• v.29 no.4
• /
• pp.275-278
• /
• 2020

In this study, we evaluated the temperature-dependent characteristics of homojunction InGaAs vertical Fin-shaped Tunnel Field-Effect Transistors (Fin TFETs), which were fabricated using a novel nano-fin patterning technique in which the Au electroplating and the high-temperature InGaAs dry-etching processes were combined. The fabricated homojunction InGaAs vertical Fin TFETs, with a fin width and gate length of 60 nm and 100 nm, respectively, exhibited excellent device characteristics, such as a minimum subthreshold swing of 80 mV/decade for drain voltage (V_DS) = 0.3 V at 300 K. We also analyzed the temperature-dependent characteristics of the fabricated TFETs and confirmed that the on-state characteristics were insensitive to temperature variations. From 77 K to 300 K, the subthreshold swing at gate voltage (V_GS) = threshold voltage (V_T), and it was constant at 115 mV/decade, thereby indicating that the conduction mechanism through band-to-band tunneling influenced the on-state characteristics of the devices.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.5
• /
• pp.508-517
• /
• 2014

We design and analyze the n-channel junctionless fin-shaped field-effect transistor (JL FinFET) with 10-nm gate length and compare its performances with those of the conventional bulk-type fin-shaped FET (conventional bulk FinFET). A three-dimensional (3-D) device simulations were performed to optimize the device design parameters including the width ($W_{fin}$) and height ($H_{fin}$) of the fin as well as the channel doping concentration ($N_{ch}$). Based on the design optimization, the two devices were compared in terms of direct-current (DC) and radio-frequency (RF) characteristics. The results reveal that the JL FinFET has better subthreshold swing, and more effectively suppresses short-channel effects (SCEs) than the conventional bulk FinFET.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.11
• /
• pp.2373-2377
• /
• 2009

In this paper, the threshold voltage characteristics have been analyzed using three dimensional Poisson's equation for FinFET. The FinFET is extensively been studing since it can reduce the short channel effects as the nano device. We have presented the short channel effects such as subthreshold swing and threshold voltage for PinFET, using the analytical three dimensional Poisson's equation. We have analyzed for channel length, thickness and width to consider the structural characteristics for FinFET. Using this model, the subthreshold swing and threshold voltage have been analyzed for FinFET since the potential and transport model of this analytical three dimensional Poisson's equation is verified as comparing with those of the numerical three dimensional Poisson's equation.