• Electrical & Electronic Materials
• /
• v.10 no.4
• /
• pp.349-354
• /
• 1997

This paper aims at studying the improvement of test method for t-weight sensitive fault (t-wsf) detect. The development of RAM fabrication technology results in not only the increase at device density on chips but also the decrease in line widths in VLSI. But, the chip size that was large and complex is shortened and simplified while the cost of chips remains at the present level, in many cases, even lowering. First of all, The testing patterns for RAM fault detect, which is apt to be complicated , need to be simplified. This new testing method made use of Local Lower Bound (L.L.B) which has the memory with the beginning pattern of 0(l) and the finishing pattern of 0(1). The proposed testing patterns can detect all of RAM faults which contain stuck-at faults, coupling faults. The number of operation is 6N at 1-weight sensitive fault, 9,5N at 2-weight sensitive fault, 7N at 3-weight sensitive fault, and 3N at 4-weight sensitive fault. This test techniques can reduce the number of test pattern in memory cells, saving much more time in test, This testing patterns can detect all static weight sensitive faults and pattern sensitive faults in RAM.

• Proceedings of the KSR Conference
• /
• 2004.06a
• /
• pp.1274-1279
• /
• 2004

This paper proposes technique to detect ground fault in railway high voltage distribution lines. Overcurrent relay technique is widely used for detecting one line ground fault that occurs most frequently in railway high voltage distribution lines. However, ground fault in distribution line is usually high impedance fault with arc. Because the fault current magnitude measured in substation is very small, the conventional overcurrent relay can't detect the high impedance ground fault. Therefore this paper proposes the advanced technique using wavelet transform. It extracts D1 component from fault signals and detects fault comparing magnitude of D1 component in each phase. To evaluate this proposed technique, we model distribution system using PSCAD/EMTDC and extract various fault data. In conclusion this technique can detect ground fault including high impedance fault regardless of fault distance, fault impedance etc.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.67 no.8
• /
• pp.1113-1118
• /
• 2018

Protection in HVDC(High Voltage Direct Current) have the very fast velocity of fault detection. Because Fault in HVDC has the fast propagation, large currents, high interruption cost. The focus to velocity caused possibility of errors like a detection error like a high impedance fault. In this paper, Proposed complex composition for get the reliability and velocity. That used SFCL(Super Conducting Fault Current Limiter), Protection Zone and DTS(Distributed Temperature Sensing). The SFCL was detect the fault by quench and DTS&Protection Zone were perceive the detect by variation too. To examine the proposed method, PSCAD/EMTDC simulated. The results of simulation, proposed methods could the detect of fault to whole HVDC line. And that improved the reliability of fault clearing.

• Transactions of the Korean Society of Mechanical Engineers B
• /
• v.41 no.11
• /
• pp.735-742
• /
• 2017

In this study, an effective model-based sensor fault detection methodology that can detect and isolate PEM temperature sensors fault is introduced. In fuel cell vehicle operation process, the stack temperature affects durability of a fuel cell. Thus, it is important for fault algorithm to detect the fault signals. The major objective of sensor fault detection is to guarantee the healthy operations of the fuel cell system and to prevent the stack from high temperature and low temperature. For the residual implementation, parity equation based on the state space is used to detect the sensors fault as stack temperature and coolant inlet temperature, and residual is compared with the healthy temperature signals. Then the residuals are evaluated by various fault scenarios that detect the presence of the sensor fault. In the result, the designed in this study fault algorithm can detect the fault signal.

• Proceedings of the KSR Conference
• /
• 2000.05a
• /
• pp.188-194
• /
• 2000

This study is about fault detection and fault area detection of LV circuit in Cab Cubicle system which have control of train to keep safety in High Speed Train. LV circuit is operated with diagnosis system like safety system. In this paper, we suggest a design and an implementation method to detect fault or to detect fault area automatically about LV circuit. The implemented system is tested successfully after implementation of some function. We expect reduction to diagnosis area or repair time by fault area module

• Aerospace Engineering and Technology
• /
• v.6 no.2
• /
• pp.150-156
• /
• 2007

In this paper, we focus on the fault detection and isolation(FDI) method for inertial navigation system with three two-degree of freedom dynamically tuned gyros(DTG) on orthogonal sensor configuration. we propose the FDI method which can detect the fault of each DTGs rather than the fault of each sensing axis. The proposed FDI method is separated into two FDI modules according to the fault magnitude in order to improve the reliability of fault detection information. For large fault detection, only instantaneous DTG measurement is used to detect a fault DTG within a short time. For small fault detection, the integrated value of DTG measurements are used to detect a fault DTG. It takes a more time to detect a fault but it serves more reliable fault detection information. Using the proposed FDI method with consideration of DTG fault characteristic, we could find out a fault DTG successfully.

• 제어로봇시스템학회:학술대회논문집
• /
• 2000.10a
• /
• pp.55-55
• /
• 2000

This paper presents a fault detection and isolation(FDI) method based on Ceneralized Likelihood Ratio(GLR) test for the tightly coupled INS/GPS. State and measurement GLR tests detect INS or GPS fault. Once the fault is detected, Multi-hypothesized GLR scheme performs the fault isolation between INS and GPS and find which satellite malfunctions. Simulation results show that the GLR method is effective enough to detect and isolate a fault of the integrated navigation system.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.7
• /
• pp.1394-1402
• /
• 1997

In this work, an efficient test algorithm and BIST architeture a for embedded memories are presented. The proposed test algorithm can fully detect stuck-at fault, transition fault, coupling fault. Moreover, the proposed test algorithm can detect nighborhood pattern sensitive fault which could not be detected in previous march test algoarithms. The proposed test algorithm perposed test algorithm performs testing for neghborhood pattern sensitive fault using backgroung data which has been used word-oriented memory testing.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.1
• /
• pp.68-79
• /
• 1998

In this paper, we propose a model-based FDI(fault detetion and isolation) algorithm to detect and isolate fault in a linear system. The proposed algorithm is gased on an HFC(hydrid fault classifier) which consists of an FCART2(fault classifier by ART2 neural network) and an FCFM(fault classifier by fault models) which operate in parallel to isolate faults. The proposed algorithm is functionally composed of three main parts-parameter estimation, fault detection, and isolation. When a change in the system occurs, the estimated parameters go through a transition zone in which errors between the system output and the stimated output and the estimated output cross a predetermined thrseshold, and in this zone the estimated parameters are tranferred to the FCART2 for fault isolation. On the other hand, once a fault in the system is detected, the FCFM statistically isolates the fault by using the error between ach fault model out put and the system output. From the computer simulation resutls, it is verified that the proposed model-based FDI algorithm can be performed successfully to detect and isolate faults in a position control system of a DC motor.

• Transactions of the Korean Society of Automotive Engineers
• /
• v.15 no.6
• /
• pp.9-16
• /
• 2007

This paper describes the design and implementation of the fault diagnosis on the Electronic Throttle Control(ETC) System. The proposed fault diagnosis consists of an input signal, actuator and a processor diagnosis. The input signal diagnosis can detect the faults of the ETC system's input signals such as the position sensor fault, source voltage fault, load current fault, and desired position fault. The actuator diagnosis is able to detect the actuator fault due to the actuator aging and an obstacle which interfere in the movement of the actuator. The processor diagnosis detects the fault which prevents the microprocessor from operating the ETC software. In order to protect the breakdown of the ETC system and assure the driving safety, appropriate reactions are also proposed according to the detected faults. The safety and reliability of the ETC system can be improved by the proposed fault diagnosis.