• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.4
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• pp.143-148
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• 2017

Flash Memory which is light and strong external shock as storage of small electronics like smartphone, digital camera, car black box has been widely used. Since the operation speed of the read operation and the write operation are different from each other, and the flash memory has the feature that it is not possible to overwrite, the delete operation is added to solve these problems. Wear-leveling must also be considered, since the number of erase times of the flash memory is limited. Many studies have been conducted on the substitutional algorithms of flash memory based on these characteristics of recent flash memories. So, to solve the problem that has existing buffer replacement algorithm this thesis divide page into 6 groups and when proposed algorithm select victim page, it consider reference page frequency and page recency.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1105-1108
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• 1999

In this paper, we propose a new addressing mode, which can be used for programmable image processor to perform image- processing algorithms effectively. Conventional addressing modes are suitable for one-dimensional data processing such as voice, but the proposed addressing mode consider two-dimensional characteristics of image data. The proposed instruction for two-dimensional addressing requires two operands to specify a pixel and doesn't require any change of memory architecture. Combining several instructions to load a pixel-data from an external memory to a register, the proposed instruction reduces code size so that satisfy hish performance and low power requirements of image processor. In addition, it uses inherent two-dimensional characteristics of image data and offers user-friendly instruction to assembler programmer.

• School Mathematics
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• v.2 no.2
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• pp.489-508
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• 2000

With the increased use of computational technology, many educators question about spending large amount of class time for dealing with computational algorithms in elementary school math classroom at the expense of more holistic aspects of mathematics such as number sense, spatial sense, problem solving and data management. This paper introduce the new method for learning addition and subtraction so called ‘Mrs. Weill’s Hill’, which is believed as a suitable remedial method for children with mathematical learning disabilities, with perceptual problems, or with limited working memory capacities. This method provides children with external memory strategies by allowing them to solve the addition and subtraction problems in a stage by stage fashion with as many steps as they require. It also gives the child greater flexibility in the solution process and thus helps reduce anxiety.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.3
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• pp.68-74
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• 2009

In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm can obtain around 1.7% BD-bitrate gain and 0.03dB BD-PSNR gain, compared with the conventional fixed-bit min-max algorithm with 37.5% memory saving.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.1
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• pp.105-113
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• 1998

A new image processor is implemented for high-speed digital copiers and facsimiles. The imgage processor performs CCD and CIS interface, pre-processing, enlargement andreduction of gray level image, and various halftoning algorithms. Implemented halftoning algorithms are simple thresholding, fuzzy based mixed mode thresholding, dithering, and edge enhanced error diffusion. The result of binarization is transferred to a printer with serial or paralel output ports. Line by line pipelined data prodessing architecture is employed with time sharing access of the external memory. In receiving mode, it converts the resolution of received binary image for compatibility with conventional facsimile. In copy mode, a line of A3 paper with 400 dpi is processed with in 2.5 ms. The prototype of image processor was implemented usig Laser Programmable Gate Array (LPGA) with 0.8.mu.m technology.

• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.3
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• pp.261-268
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• 2002

This paper represents that auto tunings of membership functions and weights in the fuzzy neural networks are effectively performed by immune algorithm. A number of hybrid methods in fuzzy-neural networks are considered in the context of tuning of learning method, a general view is provided that they are the special cases of either the membership functions or the gain modification in the neural networks by genetic algorithms. On the other hand, since the immune network system possesses a self organizing and distributed memory, it is thus adaptive to its external environment and allows a PDP (parallel distributed processing) network to complete patterns against the environmental situation. Also, it can provide optimal solution. Simulation results reveal that immune algorithms are effective approaches to search for optimal or near optimal fuzzy rules and weights.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.34-43
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• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.12
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• pp.913-917
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• 2009

Flash memories have asymmetric I/O costs for read and write in terms of latency and energy consumption. However, the ratio of these costs is dependent on the type of storage. Moreover, it is becoming more common to use two flash memories on a system as an internal memory and an external memory card. For this reason, buffer cache replacement algorithms should consider I/O costs of device as well as possibility of reference. This paper presents WWCLOCK(Write-Weighted CLOCK) algorithm which directly uses I/O costs of devices along with recency and frequency of cache blocks to selecting a victim to evict from the buffer cache. WWCLOCK can be used for wide range of storage devices with different I/O cost and for systems that are using two or more memory devices at the same time. In addition to this, it has low time and space complexity comparable to CLOCK algorithm. Trace-driven simulations show that the proposed algorithm reduces the total I/O time compared with LRU by 36.2% on average.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.48-54
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• 2010

This paper presents a high-performance architecture of integer-pel motion estimation circuit for H.264 video CODEC. Full search algorithm guarantees the best results by examining all candidate blocks. However, the full search algorithm requires a huge amount of computation and data. Many fast search algorithms have been proposed to reduce the computational efforts. The disadvantage of these algorithms is that data access from or to memory is very irregular and data reuse is difficult. In this paper, we propose an efficient integer-pixel motion estimation algorithm and the circuit architecture to improve the processing speed and reduce the external memory bandwidth. The proposed circuit supports seven kinds of variable block sizes and generates 41 motion vectors. We described the proposed high-performance motion estimation circuit at R1L and verified its operation on FPGA board. The circuit synthesized by using l30nm CMOS standard cell library processes 139.8 1080HD ($1,920{\times}1,088$) image frames per second and supports up to H.264 level 5.1.

• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.3
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• pp.246-254
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• 2002

In this paper auto-tuning scheme of PID controller based on the reference model has been studied for a Process control system by immune algorithm. Up to this time, many sophisticated tuning algorithms have been tried in order to improve the PID controller performance under such difficult conditions. Also, a number of approaches have been proposed to implement mixed control structures that combine a PID controller with fuzzy logic. However, in the actual plant, they are manually tuned through a trial and error procedure, and the derivative action is switched off. Therefore, it is difficult to tune. Since the immune system possesses a self organizing and distributed memory, it is thus adaptive to its external environment and allows a PDP (Parallel Distributed Processing) network to complete patterns against the environmental situation. Simulation results reveal that reference model basd tuning by immune network suggested in this paper is an effective approach to search for optimal or near optimal process control.