• Progress in Superconductivity and Cryogenics
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• v.2 no.2
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• pp.20-25
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• 2000

A CICC type superconducting bus-line electrically connecting a superconducting magnet to a power supply is cooled down to low temperature under the external magnetic field during operation. The thermal contraction during the cooling may be constrained by the supports which are installed to protect the bus-line from Lorenz magnetic forces. This constrained contraction causes thermal stresses in the bus-line to release thermal contraction. The minimum stress conditions in the bus-line may be optimized by controlling the supporting arrangement considering the thermal contraction and the external field. The analytical method to find optimal supports arrangement was suggested by using the beam theory, and numerical calculation using commercial code was performed to verify the suggested analytical optimization method.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.535-536
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• 2006

In the embedded system, external device interface that operates serial protocol with lower speed than the general computers is used commonly. This paper describes I2C bus protocol that is a bi-directional serial bus with a two-pin interface. The I2C bus requires a minimum amount of hardware to relay status and reliability information concerning the processor subsystem to an external device.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.49 no.9
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• pp.446-450
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• 2000

A conventional variable percentage current differential relaying algorithm for bus protection may misoperate for external faults with severe CT saturation and internal faults with high impedance. This paper proposes a percentage differential current relaying algorithm for bus protection combined with a compensating algorithm of secondary currents of CTs. Even though CTs are saturated and their secondary currents are severely distorted, the proposed relaying algorithm does not only misoperate for external faults with CT saturation but also detects the internal faults with high fault impedance. Thus, the method improves the sensitivity of the relays and does not require any counterplan for CT saturation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.4
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• pp.426-431
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• 2004

We have studied the pressure-dependent liquid crystal's dynamics in a twisted nematic (TN) liquid crystal panel with thin film transistor by applying an external pressure to it. When the external pressure is applied to the panel in a dark state, the disclination lines were generated as a light leakage whereas they did not appear in a simple test cell that has only pixel and common electrodes. It was because the disclination lines were Provoked by the electric field between pixel electrode and data/gate bus line for active matrix driving. Consequently, the external pressure resulted in dynamic instability of the liquid crystal so that the disclination lines at the data/gate bus line intruded into the active area.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.1
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• pp.44-49
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• 2003

This paper describes a percentage current differential relaying algorithm for bus protection blocked by a CT saturation detection algorithm. The detection algorithm blocks the output of a current differential relay only if a differential current is caused by CT saturation in the case of an external fault. Moreover, if a current differential relay operates faster than the detection algorithm, the blocking signal is not ignited. On the other hand. if the detection algorithm operates faster than a current differential relay, the output of the relay is blocked. The results of the simulation show that the proposed algorithm can discriminate internal faults from external faults ever when a CT is saturated in both cases. This paper concludes by implementing the algorithm into the TMS320C6701 digital signal processor. The results of hardware implementation are also satisfactory The algorithm can not only increase the sensitivity of the current differential relay but Improve the stability of the relay for an external faults.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.831-834
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• 1998

This paper describes a bus interface unit which is used in a 32bit high-performance multimedia RISC CPU including DSP unit. The main idea adopted in designing is that the bus interface unit enables the processor to provide on-chip functions for controlling memory and peripheral devices, including RAS-cAS multiplexing, DRAM refresh and parity generation and checking. The number of bus cycles used for a memory or I/O access is also defined by the processor, thus, no external bus controllers are required. All memories and peripheral devices can be connected directly, pin to pin, without any glue logic. That is the key point of the design.

• Proceedings of the KSME Conference
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• 2003.11a
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• pp.169-174
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• 2003

The thermal design of the bus bar of a Gas-Insulated Switchgear(GIS) becomes important since the current-carrying capacity of the GIS is limited by maximum operating temperature. In order to predict temperature rise of the bus bar, a program has been developed. Various heat sources possibly generated in the bus bar are calculated in the program. To estimate temperature rises at the bus bar caused by the heat balance between the heat generation and heat transfer, the finite volume method as well as the $4^{th}$ order Runge-Kutta method has been employed. In the experiments, temperature rises at conductor, contact part and external tank are measured for full-scale gas-insulated bus bars. The comparisons of the predicted values of the heat balance calculation to those of the experiments are made. From the comparisons, it is concluded that the developed program can predict the temperature rise of the bus bar quite well.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.547-550
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• 2005

This treatise studies and developed flash memory drive of ATA bus that use flash memory which is employment amount memory semiconductor to improve problem of hard-disk that is existing ATA bus. While general hard-disk is sensitive external impact or shock, but flash memory drive do save chapter as well as is strong in external impact using semiconductor memory element that disk is not low electric power, light weight possible . Practical use is expected do save chapter for embedded system or black box for vehicles, soldiers hereafter therefore.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.308-310
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• 2003

This paper proposes a percentage current differential relaying algorithm for bus protection with a compensation algorithm of a CT. The compensating algorithm estimates the core flux at the start of the first saturation based on the value of the third-difference of the secondary current. It calculates the core flux and compensates distorted currents in accordance with the magnetization curve. The test results indicate that the algorithm can discriminate internal faults from external faults when the CT saturates. It can improve not only stability of the relay in the case of an external fault but sensitivity of the relay in the case of an internal fault.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.3
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• pp.158-164
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• 2003

This paper proposes a percentage current differential relaying algorithm for bus protection using an advanced compensating algorithm of the secondary current of current transformers (CTs). The compensating algorithm estimates the core flux at the start of the first saturation based on the value of the second-difference of the secondary current. Then, it calculates the core flux and compensates distorted currents using the magnetization curve. The algorithm Is unaffected by a remanent flux. The simulation results indicate that the proposed algorithm can discriminate internal faults from external faults when the CT saturates. This paper concludes by implementing the algorithm into a TMS320C6701 digital signal processor. The results of hardware implementation are also satisfactory. The proposed algorithm can improve not only stability of the relay in the case of an external fault but sensitivity of the relay in the case of an internal fault.