• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.150-150
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• 2008

본 연구에서는 Wet chemistry damage가 Nanopatterned p-ohmic electrode에 미치는 영향을 연구하였다. Nanopattern은 Metal clustering을 이용하여, P-GaN와 Ohmic형성에 유리한 Pd을 50$\AA$ 적층한 후 Rapid Thermal Annealing방법으로 $850^{\circ}C$, $N_2$분위기에서 3min열처리를 하여 Pd Clustering mask 를 제작하였다. Wet etching은 $85^{\circ}C$, $H_3PO_4$조건에서 시간에 따라 Sample을 Dipping하는 방법으로 시행하였다 Ohmic test를 위해서 Circular - Transmission line Model 방법을 이용하였으며, Atomic Force Microscopy과 Parameter Analyzer로 Nanopatterned GaN surface위에 형성된 Ni/ Au Contact에서의 전기적 분석과, 표면구조분석을 시행하였다. AFM결과 Wet처리시간에 따라서 Etching형상 및 Etch rate이 영향을 받는 것이 확인되었고, Ohmic test에서 Wet chemistry처리에 의한 Tunneling parameter와 Schottky Barrier Height가 크게 증/감함을 관찰하였다. 이러한 결과들은 Wet처리에 의해서 발생된 Defect가 GaN의 표면과 하부에서 발생되며, Deep acceptor trap 및 transfer거동과 밀접한 관련이 있음을 확인 할 수 있었다. 보다 자세한 Transport 및 Wet chemical처리영향에 관한 형성 Mechanism은 후에 I-V-T, I-V, C-V, AFM결과 들을 활용하여 발표할 예정이다.

• Journal of the Korean Vacuum Society
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• v.13 no.3
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• pp.120-126
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• 2004

A damage-reduced trench was investigated in view of the defect distribution along trench sidewall and bottom using high resolution transmission electron microscopy, which was formed by HBr plasma and additive gases in magnetically enhanced reactive ion etching system. Adding $O_2$ and other additive gases into HBr plasma makes it possible to eliminate sidewall undercut and lower surface roughness by forming the passivation layer of lateral etching. To reduce the RIE induced damage and obtain the fine shape trench corner rounding, we investigated the hydrogen annealing effect after trench formation. Silicon atomic migration on trench surfaces using high temperature hydrogen annealing was observed with atomic scale view. Migrated atoms on crystal surfaces formed specific crystal planes such as (111), (113) low index planes, instead of fully rounded comers to reduce the overall surface energy. We could observe the buildup of migrated atoms against the oxide mask, which originated from the surface migration of silicon atoms. Using this hydrogen annealing, more uniform thermal oxide could be grown on trench surfaces, suitable for the improvement of oxide breakdown.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.178-181
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• 2003

In this work, we etched PZT films with various additive gases ($O_2$ and Ar) in $Cl_2/CF_4$ plasmas, while mixing ratio was fixed at 8/2. After the etching, the plasma induced damages are characterized in terms of hysteresis curves, leakage current, retention properties, and switching polarization. When the electrical properties of PZT etched in $O_2$ or Ar added $Cl_2/CF_4$ were compared, the value of remanent polarization in $O_2$ added $Cl_2/CF_4$ plasma is higher than that in Ar. added plasma. The maximum etch rate of the PZT thin films was 145 nm/min for 30% Ar added $Cl_2/CF_4$ gas having mixing ratio of 8/2 and 110 nm/min for 10% $O_2$ added to that same gas mixture. In order to recover the ferroelectic properties of the PZT thin films after etching, we annealed the etched PZT thin films at $550^{\circ}C$ in an $O_2$ atmosphere for 10 min. From the hysteresis curves, leakage current, retention property and switching polarization, the reduction of the etching damage and the recovery via the annealing was turned out to be more effective when $O_2$ was added to $Cl_2/CF_4$ than Ar. X-ray diffraction (XRD) showed that the structural damage was lower when $O_2$ was added to $Cl_2/CF_4$. And the improvement in the ferroelectric properties of the annealed samples was consistent with the increased intensities of the (100) and the (200) PZT peaks.

• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.35-39
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• 2019

Effect of Ge₂Sb₂Te₅ (GST) chalcogen composition on plasma induced damage was investigated by using Ar ions and F radicals. Experiments were carried out with three different modes; the physical etching, the chemical etching, and the ion-enhanced chemical etching mode. For the physical etching by Ar ions, the sputtering yield was obtained according to ion bombarding energy and there was no change in GST composition ratio. In the plasma mode, the lowest etch rate was measured at the same applied power and there was also no plasma induced damage. In the ion-enhanced chemical etching conditions irradiated with high energy ions and F halogen radicals, the GST composition ratio was changed according to the density of F radicals, resulting in higher roughness of the etched surface. The change of GST composition ratio in halogen plasma is caused by the volatility difference of GST-halogen compounds with high energy ions over than the activation energy of surface reactions.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.7
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• pp.570-575
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• 2002

$SrBi_2Ta_2O_9$ thin films were etched in $Cl_2/CF_4/Ar$ inductively coupled plasma (ICP). The maximum etch rate was 1300 ${\AA}/min$ at 900 W ICP power in Cl$_2$(20%)/$CF_4$(20%)/Ar(60%). As RF source power increased, radicals (F, Cl) and ion ($Ar^+$) increased. The influence of plasma induced damage during etching process was investigated in terms of P-E hysteresis loops, chemical states on the surface, surface morphology and phase of X-ray diffraction. The chemical states on the etched surface were investigated with X-ray spectroscopy and secondary ion mass spectrometry. After annealing $700^{\circ}C$ for 1 h in $O_2$ atmosphere, the decreased P-E hysteresises of the etched SBT thin films in Ar and $Cl_2/CF_4/Ar$ plasma were recovered.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.4
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• pp.325-331
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• 2007

In this study, the inter-metal dielectric material of FSG was changed by low-k material in $0.13{\mu}m$ foundry-compatible technology (FCT) device process based on fluorinated silicate glass (FSG). Black diamond (BD) was used as a low-k material with a dielectric constant of 2.95 for optimization and yield-improvement of the low-k based device process. For yield-improvement in low-k based device process, some problems such as photoresist (PR) poisoning, damage of low-k in etch/ash/cleaning process, and chemical mechanical planarization (CMP) delamination must be solved. The PR poisoning was not observed in BD based device. The pressure in CMP process decreased to 2.8 psi to remove the CMP delamination for Cu-CMP and USG-CMP. $H_2O$ ashing process was selected instead of $O_2$ ashing process due to the lowest condition of low-k damage. NE14 cleaning after ashing process lot the removal of organic residues in vias and trenches was employed for wet process instead of dilute HF (DHF) process. The similar-state of SRAM yield was obtained in Cu/low-k process compared with the conventional $0.13{\mu}m$ FCT device by the optimization of these process conditions.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.14 no.2
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• pp.47-49
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• 2004

Gate protection $SiN_x$ as an alternative to a conventional re-oxidation process in Dynamic Random Access Memory devices is investigated. This process can not only protect the gate electrode tungsten against oxidation, but also save the thermal budget due to the re-oxidation. The protection $SiN_x$ process is applied to the poly-Si gate, and its device performance is measured and compared with the re-oxidation processed poly-Si gate. The results on the gate dielectric integrity show that etch damage-curing capability of protection $SiN_x$ is comparable to the re-oxidation process. In addition, the hot carrier immunity of the $SiN_x$ deposited gate is superior to that of re-oxidation processed gate.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.4
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• pp.361-365
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• 2003

A unipolar-type E-chuck was fabricated for the application of holding silicon wafers in the oxide etcher. For the fabrication of the unipolar ESC, core technologies such as coating of polyimide films and anodizing treatment of aluminum surface were developed. The polyimide films were prepared on thin coated copper substrates to minimize the plasma damage during the etch processing. Thin film heater technology was also developed for new type of E-chuck.

• Current Photovoltaic Research
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• v.5 no.4
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• pp.105-108
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• 2017

The reactive ion etching (RIE) technology which enables nano-texturatization of surface is applied on monocrystalline silicon solar cell. The additional RIE process on alkalized textured surface further improves the blue response and short circuit current. Such parameter is characterized by surface reflectance and quantum efficiency measurement. By varying the RIE process time and matching the subsequent processes, the absolute efficiency gain of 0.13% is achieved. However, the result indicates potential efficiency gain could be higher due to process integration. The critical etch process time is discussed which minimizes both front surface reflectance and etching damage, considering the challenges of required system throughput in industry.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.77-81
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• 2020

Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.