• Title/Summary/Keyword: encoder optimization

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Advanced Real-Time Rate Control for Low Bit Rate Video Communication

  • Kim, Yoon
    • Journal of the Korea Computer Industry Society
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    • v.7 no.5
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    • pp.513-520
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    • 2006
  • In this paper, we propose a novel real-time frame-layer rate control algorithm using sliding window method for low bit rate video coding. The proposed rate control method performs bit allocation at the frame level to minimize the average distortion over an entire sequence as well as variations in distortion between frames. A new frame-layer rate-distortion model is derived, and a non-iterative optimization method is used for low computational complexity. In order to reduce the quality fluctuation, we use a sliding window scheme which does not require the pre-analysis process. Therefore, the proposed algorithm does not produce time delay from encoding, and is suitable for real-time low-complexity video encoder. Experimental results indicate that the proposed control method provides better visual and PSNR performance than the existing TMN8 rate control method.

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Fast Intra-Prediction Mode Decision Algorithm for H.264/AVC using Non-parametric Thresholds and Simplified Directional Masks

  • Kim, Young-Ju
    • Journal of information and communication convergence engineering
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    • v.7 no.4
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    • pp.501-506
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    • 2009
  • In the H.264/ AVC video coding standard, the intra-prediction coding with various block sizes offers a considerably high improvement in coding efficiency compared to previous standards. In order to achieve this, H.264/AVC uses the Rate-distortion optimization (RDO) technique to select the best intraprediction mode for a macroblock, and it brings about the drastic increase of the computation complexity of H.264 encoder. To reduce the computation complexity and stabilize the coding performance on visual quality, this paper proposed a fast intra-prediction mode decision algorithm using non-parametric thresholds and simplified directional masks. The use of nonparametric thresholds makes the intra-coding performance not be dependent on types of video sequences and simplified directional masks reduces the compuation loads needed by the calculation of local edge information. Experiment results show that the proposed algorithm is able to reduce more than 55% of the whole encoding time with a negligible loss in PSNR and bitrates and provides the stable performance regardless types of video sequences.

Control and data analysis of a measuring machine for cams (캠 형상 전용 측정기 제어 및 해석 S/W 개발)

  • 최동우;강재관
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1997.10a
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    • pp.150-153
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    • 1997
  • In this paper, a control and data analysis S/W of a dedicated measuring machine for cams is developed. A rotary encoder is employed to measure the angular displacement of the motor, and a linear scale does the linear displacement of the prove. The design and measuring data are interpolated by cubic spline curves respectively to compute the error which is defined by the maximum distance between two curves. Further, optimization module to find the exact error is also developed to remove the error occurred due initial measuring position. The developed system takes only 6 minutes to measure the cam and to analyze the measuring data while the CMM takes about 1 hours even with a skilled operator.

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Fast Intra Mode Decision using Transform Coefficients (변환 계수를 이용한 고속 인트라모드 결정법)

  • Hwang Gyu-Yong;Park Jong-Bin;Jeon Byeung-Woo
    • 한국정보통신설비학회:학술대회논문집
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    • 2006.08a
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    • pp.255-258
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    • 2006
  • In the H.264/AVC standard, intra prediction increases the coding efficiency of intra macroblocks and by applying rate-distortion optimization to each macroblock, it is possible to choose Inter or Intra encoding adaptively. This sort of encoding scheme, however, increases encoding complexity dramatically and causes troubles in practical applications of the real-time mobile environment. In order to decrease the complexity, variety of methods is proposed but most of those take only its current block into consideration for selecting candidate modes which naturally causes degradation in PSNR (Peak Signal to Noise Ratio). The proposed fast intra mode decision finds the candidate modes by analyzing transformed coefficients of neighboring blocks stored in the buffer at the encoder stage of input sequences. We verify this proposed scheme in complexity, PSNR and bit-rate.

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Implementing Design Space Exploration Simulation tool for Real-Time Reconfiguration System (실시간 재구성 시스템을 위한 설계 공간 탐색 시뮬레이션 도구 구현)

  • Ahn, Seong-Youg;Lee, Byeong-Seok;Lee, Jeong-A
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.571-572
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    • 2006
  • A simulation tool for design space exploration of a real-time reconfiguration system was developed in this paper. We described an algorithm for a partial real-time reconfiguration to utilize already existing configured functional units and applied it to H.263 encoder application. This scheme allows us to find a starting configuration for the further optimization without actually building a prototype.

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Relative SATD-based Minimum Risk Bayesian Framework for Fast Intra Decision of HEVC

  • Gwon, Daehyeok;Choi, Haechul
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.13 no.1
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    • pp.385-405
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    • 2019
  • High Efficiency Video Coding (HEVC) enables significantly improved compression performance relative to existing standards. However, the advance also requires high computational complexity. To accelerate the intra prediction mode decision, a minimum risk Bayesian classification framework is introduced. The classifier selects a small number of candidate modes to be evaluated by a rate-distortion optimization process using the sum of absolute Hadamard transformed difference (SATD). Moreover, the proposed method provides a loss factor that is a good trade-off model between computational complexity and coding efficiency. Experimental results show that the proposed method achieves a 31.54% average reduction in the encoding run time with a negligible coding loss of 0.93% BD-rate relative to HEVC test model 16.6 for the Intra_Main common test condition.

Dependent Quantization for Scalable Video Coding

  • Pranantha, Danu;Kim, Mun-Churl;Hahm, Sang-Jin;Lee, Keun-Sik;Park, Keun-Soo
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2006.11a
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    • pp.127-132
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    • 2006
  • Quantization in video coding plays an important role in controlling the bit-rate of compressed video bit-streams. It has been used as an important control means to adjust the amount of bit-streams to at]owed bandwidth of delivery networks and storage. Due to the dependent nature of video coding, dependent quantization has been proposed and applied for MPEG-2 video coding to better maintain the quality of reconstructed frame for given constraints of target bit-rate. Since Scalable Video Coding (SVC) being currently standardized exhibits highly dependent coding nature not only between frames but also lower and higher scalability layers where the dependent quantization can be effectively applied, in this paper, we propose a dependent quantization scheme for SVC and compare its performance in visual qualities and bit-rates with the current JSVM reference software for SVC. The proposed technique exploits the frame dependences within each GOP of SVC scalability layers to formulate dependent quantization. We utilize Lagrange optimization, which is widely accepted in R-D (rate-distortion) based optimization, and construct trellis graph to find the optimal cost path in the trellis by minimizing the R-D cost. The optimal cost path in the trellis graph is the optimal set of quantization parameters (QP) for frames within a GOP. In order to reduce the complexity, we employ pruning procedure using monotonicity property in the trellis optimization and cut the frame dependency into one GOP to decrease dependency depth. The optimal Lagrange multiplier that is used for SVC is equal to H.264/AVC which is also used in the mode prediction of the JSVM reference software. The experimental result shows that the dependent quantization outperforms the current JSVM reference software encoder which actually takes a linear increasing QP in temporal scalability layers. The superiority of the dependent quantization is achieved up to 1.25 dB increment in PSNR values and 20% bits saving for the enhancement layer of SVC.

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An MPEG-2 AAC Encoder Chip Design Operating under 70MIPS (70MIPS 이내에서 동작하는 MPEG-2 AAC 부호화 칩 설계)

  • Kang Hee-Chul;Park Ju-Sung;Jung Kab-Ju;Park Jong-In;Choi Byung-Gab;Kim Tae-Hoon;Kim Sung-Woo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.4 s.334
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    • pp.61-68
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    • 2005
  • A chip, which can fast encoder the audio data to AAC (Advanced Audio Coding) LC(Low Complexity) that is MPEG-2 audio standard, has been designed on the basis of a 32 bits DSP core and fabricated with 0.25um CMOS technology. At first, the various optimization methods for implementing the algerian are devised to reduce the memory size and calculation cycles. FFT(Fast Fourier Transform) hardware block is added to the DSP core to get the more reduction of the calculation cycles. The chips has the size of $7.20\times7.20 mm^2$ and about 830,000 equivalent gates, can carry out AAC encoding under 70MIPS(Million Instructions per Second).

Real-time Implementation of the G.729 Annex A Using ARM9 $Thumb^{\circledR}$ Processor Core (ARM9 $Thumb^{\circledR}$ 프로세서 코어를 이용한 G.729A의 실시간 구현)

  • 성호상;이동원
    • The Journal of the Acoustical Society of Korea
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    • v.20 no.7
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    • pp.63-68
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    • 2001
  • This paper describes the details of ITU-T SGIS G.729A speech coder implementation using ARM9 Thumb/sup R/ processor core and various techniques used in the optimization process. ITU-T G.729 speech coder is the standard of the toll quality 8 kbit/s speech coding. The input to the speech encoder is assumed to be a 16 bits PCM signal at a sampling rate of 8000 samples per second. G.729A is reduced complexity version of the G.729 coder. This version is bit stream interoperable with the full version. The implemented coder requires 34.8 MIPS for the encoder and 8.1 MIPS for the decoder, 36.5 kBytes of program ROM and 6.3 kBytes of data RAM, respectively. The implemented coder is tested against the set of 9 test vectors provided by ITU-T for bit exact implementation.

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Optimization of H.264 Encoder based on Hardware Implementation in Embedded System (임베디드시스템 환경에서 하드웨어 기반 H.264 Encoder 최적화)

  • Cho, Jung-Hyun;Lee, Myung-Soo;Jeong, Han-Soo;Kim, Chang-Suk;Cho, Dae-Jea
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.11 no.8
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    • pp.3076-3082
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    • 2010
  • The techniques and the products which use various video compression codec are come out from army or civil field. In existing high-end PC environment, process of the video compression codec does not become a problem, but in embedded system environments which limited system resources, because the system load due to the high-resolution images compressed by high-density, issues of performance and utilization are highlighted. This paper proposes the DirectShow Filter interfaces which are a hardware method in order to solve the problem existing software algorithms for image compression performance and peripheral interfaces.