• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.318-321
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• 2002

This paper presents a proper condition to achieve high conversion efficiency using PC1D simulator on sri-crystalline Si solar cells. Various efficiency influencing parameters such as rear surface recombination velocity and minority carrier diffusion length in the base region, front surface recombination velocity, junction depth and doping concentration in the Emitter layer, BSF thickness and doping concentration were investigated. Optimized cell parameters were given as rear surface recombination of 1000 cm/s, minority carrier diffusion length in the base region 200 $\mu\textrm{m}$, front surface recombination velocity 100 cm/s, sheet resistivity of emitter layer 100 Ω/$\square$, BSF thickness 5 $\mu\textrm{m}$, doping concentration 5${\times}$10$\^$19/ cm$\^$-3/. Among the investigated variables, we learn that a diffusion length of base layer acts as a key factor to achieve conversion efficiency higher than 19 %.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.590-590
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• 2012

A transparent conducting oxide (TCO) layer was applied in crystalline Si (c-Si) solar cells without use of the conventional SiNx-coating. A high quality indium-tin-oxide (ITO) layer was directly deposited on an emitter layer of a Si wafer. Three different types of emitters were formed by controlling the phosphorous diffusion condition. A light-doped emitter forming a thinner emitter junction showed an improved photoconversion efficiency of 14.1% comparing to 13.2% of a heavy-doped emitter. This was induced by lower recombination within a narrower depletion region of the light-doped emitter. In the aspect of light management, the intermediate refractive index of ITO is effective to reduce the light reflection leading the enhanced carrier generation in a Si absorber. For the electrical aspect, the ITO layer serves as an efficient electrical conductor and thus relieves the burden of high contact resistance of the light-doped emitter. Additionally, the ITO works as a buffer layer of Ag and Si and certainly prevents the shunting problem of Ag penetration into Si emitter region. It discusses an efficient design scheme of TCO-embedded emitter Si solar cells.

• 한국태양에너지학회:학술대회논문집
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• 2011.11a
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• pp.56-59
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• 2011

The process conditions for high efficiency industrial crystalline Si solar cells with selective emitter were optimized. In the screen printed solar cells, the sheet resistance must be 50-60V/sq. because of metal contact resistance. But the low sheet resistance causes the increase of the recombination and blue response at the short wavelength. Therefore, the screen printed solar cells with homogeneous emitter have limitations of efficiency, and this means that the selective emitter must be used to improve cell efficiency. This work demonstrates the feasibility of a commercially available selective emitter process, based on screen printing and conventional diffusion process. Now, we improved cell efficiency from 18.29% to18.45% by transition of heavy emitter pattern and shallow emitter doping condition.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.236-236
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• 2010

단일접합 $n^+-p/p^+$ (p-emitter) 및 $p^+-n/n^+$ (n-emitter) GaAs 태양전지 (Solar Cell)를 각각 제작하여, 그 소자특성을 비교 분석하였다. AM 1.5 (1 sun, $100\;mW/cm^2$) 표준광을 조사할 경우, p-emitter/n-emitter 소자의 개방회로전압 (Voc), 단락회로전류 (Jsc), 충전율 (FF), 효율 (Eff)은 각각 0.910/0.917 V, $15.9/16.1\;mA/cm^2$, 78.7/78.9, 11.4/12.1%로서, n-emitter 소자가 다소 크지만 거의 비슷한 값을 가지고 있었다. 태양전지의 집광 특성을 분석하기 위하여 조사광의 출력에 따른 태양전지의 소자 특성을 측정하였다. 조사광 강도가 높아짐에 따라 p-emitter 소자의 특성은 점진적으로 증가하는 반면, n-emitter는 1.3 sun에서 약 1.4 배의 최대 효율 (17%)을 나타내고 조사광이 더 증가함에 따라 급격히 감소하는 특성을 보여 주었다. (그림 참고) 본 연구에서 사용한 2종류 소자의 층구조는 서로 반대되는 대칭구조로서, 모두 가까이에 위치하고 있는 표면전극 (surface finger) 방향으로 소수전하 (minority carrier)가 이동하고 다수전하 (majority carrier)는 기판 (두께 $350\;{\mu}m$)을 통한 먼 거리의 후면전극 (back electrode)으로 표류 (drift)되도록 설계되어 있다. 이때, n-emitter에서는 이동도 (mobility)와 확산길이 (diffusion length)가 높은 전자가 후면전극으로 이동하기 때문에 적정밀도의 전자-정공 쌍 (EHP)이 여기될 경우에는 Jsc와 Eff가 극대화되지만, 조사광 강도 또는 EHP가 더 높아질 경우에는 직렬저항의 증가와 함께 전류-전압 (I-V)의 이상인자 (ideality factor)가 커짐으로서 FF와 효율이 급격히 감소한 결과로 분석된다. 현재 전산모사를 통한 자세한 분석을 진행하고 있으며, 본 결과는 효율 극대화를 위한 최적 층구조 및 도핑 밀도 설계에 활용할 수 있을 것으로 판단된다.

• Current Photovoltaic Research
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• v.2 no.4
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• pp.147-151
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• 2014

A boron doping process using a boron tri-bromide ($BBr_3$) as a boron source was applied to form a $p^+$ emitter layer on an n-type mono-crystalline CZ substrate. Nitrogen ($N_2$) gas as an additive of the diffusion process was varied in order to study the variations in sheet resistance and the uniformity of doped layer. The flow rate of $N_2$ gas flow was changed in the range 3 slm~10 slm. The sheet resistance uniformity however was found to be variable with the variation of the $N_2$ flow rate. The optimal flow rate for $N_2$ gas was found to be 4 slm, resulting in a sheet resistance value of $50{\Omega}/sq$ and having a uniformity of less than 10%. The process temperature was also varied in order to study its influence on the sheet resistance and minority carrier lifetimes. A higher lifetime value of $1727.72{\mu}s$ was achieved for the emitter having $51.74{\Omega}/sq$ sheet resistances. The thickness of the boron rich layer (BRL) was found to increase with the increase in the process temperature and a decrease in the sheet resistance was observed with the increase in the process temperature. Furthermore, a passivated emitter solar cell (PESC) type solar cell structure comprised of a boron doped emitter and phosphorus doped back surface field (BSF) having Ni/Cu contacts yielding 15.32% efficiency is fabricated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.553-556
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• 1999

This paper presents a proper condition to achieve above 19 % conversion efficiency using PC1D simulator. Cast poly-Si wafers with resistivity of 1 $\Omega$-cm and thickness of 250 ${\mu}{\textrm}{m}$ were used as a starting material. Various efficiency influencing parameters such as rear surface recombination velocity and minority carrier diffusion length in the base region, front surface recombination velocity, junction depth and doping concentration in the Emitter layer, BSF thickness and doping concentration were investigated. Optimized cell parameters were given as rear surface recombination of 1000 cm/s, minority carrier diffusion length in the base region 200 ${\mu}{\textrm}{m}$, front surface recombination velocity 100 cnt/s, sheet resistivity of emitter layer 100 $\Omega$/$\square$, BSF thickness 5 ${\mu}{\textrm}{m}$, doping concentration 5$\times$10$^{19}$ cm$^3$ . Among the investigated variables, we learn that a diffusion length of base layer acts as a key factor to achieve conversion efficiency higher than 19 %. Further details of simulation parameters and their effects to cell characteristics are discussed in this paper.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.4
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• pp.263-270
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• 2020

In this study, the physical mechanism and diffusion effects in aluminium implanted silicon was investigated. For fabricating power semiconductor devices, an aluminum implantation can be used as an emitter and a long drift region in a power diode, transistor, and thyristor. Thermal treatment with O₂ gas exhibited to a remarkably deeper profile than inert gas with N₂ in the depth of junction structure. The redistribution of aluminum implanted through via thermal annealing exhibited oxidation-enhanced diffusion in comparison with inert gas atmosphere. To investigate doping distribution for implantation and diffusion experiments, spreading resistance and secondary ion mass spectrometer tools were used for the measurements. For the deep-junction structure of these experiments, aluminum implantation and diffusion exhibited a junction depth around 20 ㎛ for the fabrication of power silicon devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.480.1-480.1
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• 2014

In this study, we suggest the new emitter formation applied solid phase epitaxy (SPE) growth process using rapid thermal process (RTP). Preferentially, we describe the SPE growth of intrinsic a-Si thin film through RTP heat treatment by radio-frequency plasma-enhanced chemical vapor deposition (RF-PECVD). Phase transition of intrinsic a-Si thin films were taken place under $600^{\circ}C$ for 5 min annealing condition measured by spectroscopic ellipsometer (SE) applied to effective medium approximation (EMA). We confirmed the SPE growth using high resolution transmission electron microscope (HR-TEM) analysis. Similarly, phase transition of P doped a-Si thin films were arisen $700^{\circ}C$ for 1 min, however, crystallinity is lower than intrinsic a-Si thin films. It is referable to the interference of the dopant. Based on this, we fabricated 16.7% solar cell to apply emitter layer formed SPE growth of P doped a-Si thin films using RTP. We considered that is a relative short process time compare to make the phosphorus emitter such as diffusion using furnace. Also, it is causing process simplification that can be omitted phosphorus silicate glass (PSG) removal and edge isolation process.

• Current Photovoltaic Research
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• v.2 no.3
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• pp.130-134
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• 2014

We have fabricated the selective emitter solar cell using double textured nanowires structure. The $40{\times}40mm2$-sized silicon substrates were textured to form the pyramid-shaped surface and the nanowires were fabricated by metal assisted chemical etching process using Ag nanoparticles, subsequently. The heavily doped and shallow emitters for selectiv eemitter solar cells were prepared through the thermal $POCl_3$ diffusion and chemical etch-back process, respectively. The front and rear electrodes were prepared following conventional screen printing method and the widths of fingers have been optimized. The selective emitter solar cell using double textured nanowires structure achieved a conversion efficiency of 17.9% with improved absorption and short circuit current density.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.5
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• pp.366-370
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• 2019

In this paper, a single N+ emitter trench gate-type insulated gate bipolar transistor (IGBT) device was studied using T-CAD, in order to achieve a low on-state voltage drop (Vce-sat) and high breakdown voltage, which would reduce power loss and device reliability. Using the simulation, the threshold voltage, breakdown voltage, and on-state voltage drop were studied as a function of the temperature, the length of time in the diffusion process (drive-in) after implant, and the trench gate depth. During the drive-in process, a $20^{\circ}C$ change in temperature from 1,000 to $1,160^{\circ}C$ over a 150 minute time frame resulted in a 1 to 4 V change in the threshold voltage and a 24 to 2.6 V change in the on-state voltage drop. As a result, a 0.5 um change in the trench depth of 3.5 to 7.5 um resulted in the breakdown voltage decreasing from 802 to 692 V.