• Title/Summary/Keyword: embedded design

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Assessment of Optimum Reinforcement of Rebar for Joint of PHC Pile and Foundation Plate (고강도 콘크리트 말뚝과 기초판 접합부의 최적 철근보강량 산정)

  • Park, Jong-Bae;Sim, Young-Jong;Chun, Young-Soo;Park, Seong-Sik;Park, Yong-Boo
    • Land and Housing Review
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    • v.1 no.1
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    • pp.67-73
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    • 2010
  • Method of protruding steel bar embedded in PHC pile for connecting with foundation plate is an intermediate form of fixed and hinged connection and has often been used in architectural structures such as apartment complex. However, mechanical properties of this method have not been proved and its construction process is not simple. In this study, therefore, by analyzing previous research and by considering ratio of steel bar and concrete in PHC pile, which is minimum reinforcement of rebar, the newly optimized method of reinforcing joint of PHC pile and foundation plate is suggested with respect to PHC pile type (PHC 450, PHC 500, and PHC 600). To assess mechanical properties (ultimate tensile and shear strength) of joint of PHC pile and foundation plate, full scale experimental tests are performed. As a result, all cases are satisfied with required design criteria and can be practically applied. Our results indicate that reduction of rebar reinforcement compared to previous method would lead cost saving in PHC pile construction.

Calculation of Base Load Capacity of Bored Pre-cast Piles Using New PHC PIles with Steel Pipe at Pile Toe (강관 부착 PHC파일로 시공된 매입말뚝의 선단지지력 산정)

  • Paik, Kyu-Ho
    • Journal of the Korean Geotechnical Society
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    • v.32 no.9
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    • pp.5-16
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    • 2016
  • New PHC piles, where short steel pipes are attached to the pile toe, are developed to increase the base load capacity of bored pre-cast piles embedded in weathered rock. In this study, new bored pre-cast piles using the new PHC piles are installed at 7 test sites with different soil conditions, and static and dynamic pile load tests are performed to investigate quantitative characteristics on the base load capacity of new bored pre-cast piles. In addition, based on the static pile load test results, a new empirical equation for estimating the base load capacity of new bored pre-cast piles is proposed. A comparison between predicted and measured base load capacities shows that the proposed empirical equation produces conservative predictions for the new bored pre-cast piles. However, the existing design criterion significantly underestimates the base load capacity of new bored pre-cast piles.

Design of Lightweight Artificial Intelligence System for Multimodal Signal Processing (멀티모달 신호처리를 위한 경량 인공지능 시스템 설계)

  • Kim, Byung-Soo;Lee, Jea-Hack;Hwang, Tae-Ho;Kim, Dong-Sun
    • The Journal of the Korea institute of electronic communication sciences
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    • v.13 no.5
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    • pp.1037-1042
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    • 2018
  • The neuromorphic technology has been researched for decades, which learns and processes the information by imitating the human brain. The hardware implementations of neuromorphic systems are configured with highly parallel processing structures and a number of simple computational units. It can achieve high processing speed, low power consumption, and low hardware complexity. Recently, the interests of the neuromorphic technology for low power and small embedded systems have been increasing rapidly. To implement low-complexity hardware, it is necessary to reduce input data dimension without accuracy loss. This paper proposed a low-complexity artificial intelligent engine which consists of parallel neuron engines and a feature extractor. A artificial intelligent engine has a number of neuron engines and its controller to process multimodal sensor data. We verified the performance of the proposed neuron engine including the designed artificial intelligent engines, the feature extractor, and a Micro Controller Unit(MCU).

A 250MS/s 8 Bit CMOS folding and Interpolating AD Converter with 2 Stage Architecture (2단 구조를 사용한 250MS/s 8비트 CMOS 폴딩-인터폴레이팅 AD 변환기)

  • 이돈섭;곽계달
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.4
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    • pp.826-832
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    • 2004
  • A CMOS 8 bit folding and interpolating ADC for an embedded system inside VLSI is presented in this paper. This folding ADC uses the 2 stage architecture for improving of nonlinearity. repeating the folding and interpolating twice. At a proposed structure, a transistor differential pair operates on the second folder. A ADC with 2 stage architecture reduces the number of comparators and resisters. So it is possible to provide small chip size, low power consumption and high operating speed. The design technology is based on fully standard 0.25m double-Poly 2 metal n-well CMOS Process. The simulated Power consumption is 45mW with an applied voltage of 2.5V and sampling frequency of 250MHz. The INL and DNL are within <ㅆㄸㅌ>$\pm$0.2LSB, respectively. The SNDR is approximately 45dB for input frequency of 10MHz.

Sustain Driver and Reset Circuit for Plasma Display (플라즈마 디스플레이를 위한 서스테인 및 리셋 회로)

  • Kang, Feel-Soon;;Park, Jin-Hyun
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.2
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    • pp.685-688
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    • 2005
  • An efficient sustain driver and a useful reset circuit composition technique are proposed for plasma display panel drive. The proposed sustain driver uses a series resonance between an external inductor and a panel to recover the energy dissipated by a capacitive displacement current of PDP. It consists of four switching devices, an inductor, and external capacitors, which supply sustain voltage sources. Although the amplitude of an input voltage source is twice as high as that of conventional sustain drivers, average voltage stress imposed on power switching devices is nearly same in their values. Moreover, the input voltage source can be directly applied for the use of a reset voltage source. Owing to this scheme, the proposed sustain driver and the embedded reset circuit have a simple configuration. The operational principle and design example are given with theoretical analyses. The validity of the proposed drive system is verified through experiments using a prototype equipped with a 7.5-inch-diagonal AC plasma display panel.

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Hardware Design of AES Cryptography Module Operating as Coprocessor of Core-A Microprocessor (Core-A 마이크로프로세서의 코프로세서로 동작하는 AES 암호모듈의 하드웨어 설계)

  • Ha, Chang-Soo;Choi, Byeong-Yoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.12
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    • pp.2569-2578
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    • 2009
  • Core-A microprocessor is the all-Korean product designed as 32-bit embedded RISC microprocessor developed by KAIST and supported by the Industrial Property Office. This paper analyze Core-A microprocessor architecture and proposes efficient method to interface Core-A microprocessor with coprocessor. To verify proposed interfacing method, the AES cryptography processor that has 128-bit key and block size is used as a coprocessor. Coprocessor and AES are written in Verilog-HDL and verified using Modelsim simulator. It except AES module consists of about 3,743 gates and its maximum operating frequency is about 90Mhz under 0.35um CMOS technology. The proposed coprocessor interface architecture is efficiency to send data or to receive data from Core-A to coprocessor.

Performance Evaluation of I/O Intensive Stress Test in Cluster File System SANiqueTM (집중적인 입출력 스트레스 테스트를 통한 클러스터 파일 시스템 SANiqueTM의 성능평가)

  • Lee, Kyu-Woong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.2
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    • pp.415-420
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    • 2010
  • This paper describes the design overview of shared file system $SANique^{TM}$ and analyzes the performance evaluation results of I/O intensive stress test based on various cluster file system architectures. Especially, we illustrate the performance analysis for the comparison results between the $SANique^{TM}$ and the Linux file system EXT3 system that is used to generally in Unix world. In order to perform our evaluation, Oracle 10g database system is operated on the top of cluster file system, and we developed the various kinds of testing tools which are compiled by ESQL/C from Oracle. Three types of architectures are used in this performance evaluation. Those are the cluster file system $SANique^{TM}$, EXT3 and the combined architecture of $SANique^{TM}$ and EXT3. In this paper, we present that the results of $SANique^{TM}$ outperforms other cluster file systems in the overhead for providing the true sharing over the connecting server nodes.

Implementation of oral patient management system using smartphone and embedded imaging module (스마트폰과 임베디드 촬영 모듈을 활용한 구강 환자 관리 시스템 구현)

  • Lee, Hyoun-sup;Youn, Joo-sang;Kim, Jin-deog
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.22 no.4
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    • pp.581-586
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    • 2018
  • A common characteristic of many patients whose illness is getting worse is that they miss the treatment red flag. When high subjective symptoms appear or there is no strong pain, this problem arises because it is reluctant to visit the hospital. Gingivitis causes bleeding from the gums in the early and mid-term, and shows mild symptoms of tooth collapse. When treatment is done at this point, it shows a very high effect. However, when you miss the timing of treatment you will have a situation where you can't eat food by causing serious problems in the health of the gums and oral cavity. In this paper, the patient's periodontal image is photographed with a smartphone and transmitted in real time. This is done by the doctor in charge. Then, we propose a design of a patient management system that provides information on the current situation to the patient so as not to miss the timing of treatment.

Design and Inplementation of S/W for a Davinci-based Smart Camera (다빈치 기반 스마트 카메라 S/W 설계 및 구현)

  • Yu, Hui-Jse;Chung, Sun-Tae;Jung, Souhwan
    • Proceedings of the Korea Contents Association Conference
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    • 2008.05a
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    • pp.116-120
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    • 2008
  • Smart Camera provides intelligent vision functionalities which can interpret captured video, extract context-aware information and execute a necessary action in real-timeliness in addition to the functionality of network cameras which transmit the compressed acquired videos through networks. Intelligent vision algorithms demand tremendous computations so that real-time processing of computation of intelligent vision algorithms as well as compression and transmission of videos simultaneously is too much burden for a single CPU. Davinci processor of Texas Instruments is a popular ASSP(Application Specific Standard Product) which has dual core architecture of ARM core and DSP core and provides various I/O interfaces as well as networking interface and video acquiring interface necessary for developing digital video embedded applications. In this paper, we report the results of designing and implementing S/W for Davinci-based smart camera. We implement a face detection as an example of vision application and verify the implementation works well. In the future, for the development of a smart camera with more broad and real-time vision functionalities, it is necessary to study about more efficient vision application S/W architecture and optimization of vision algorithms on DSP core of Davichi processor.

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Development of USLExls and its Application for the Analysis of the Impact of Soil-Filling Work on Soil Loss (USLExls를 이용한 복토법에 따른 필지 단위 토양유실량 분석)

  • Kim, Sorae;Yu, Chan;Lee, Sang-Whan;Ji, Won-Hyun;Jang, Min-Won
    • Journal of The Korean Society of Agricultural Engineers
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    • v.59 no.6
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    • pp.109-125
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    • 2017
  • This study aimed to develop a parcel-unit soil loss estimation tool embedded in Excel worksheet, USLExls, required for the design of contaminated farmland restoration project and to analyze the impact of the project carried out soil-filling work on soil loss. USLE method was adopted for the estimation of average annual soil loss in a parcel unit, and each erosivity factor in the USLE equation was defined through the review of previous studies. USLExls was implemented to allow an engineer to try out different combinations just by selecting one among the popular formulas by each factor at a combo box and to simply update parameters by using look-up tables. This study applied it to the estimation of soil loss before and after soil-filling work at Dong-a project area. The average annual soil loss after the project increased by about 2.4 times than before on average, and about 60 % of 291 parcels shifted to worse classes under the classification criteria proposed by Kwak (2005). Although average farmland steepness was lower thanks to land grading work, the soil loss increased because the inappropriate texture of the cover soil induced the soil erosion factor K to increase from 0.33 before to 0.78 after the soil-filling work. The results showed that the selection of cover soil for soil-filling work should be carefully considered in terms soil loss control and the estimation of change in soil loss should be mandatory in planning a contaminated farmland restoration project.