• Proceedings of the Korean Vacuum Society Conference
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• 1997.02a
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• pp.213-214
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• 1997

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.1028-1034
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• 1989

A method of analysis of the steady-state performance of induction motor with supply voltage controlled by cyclically-triggered inline thyristors is presented. Phase-variable model and asymmetrical components are not used in this analysis. Instead, Fast Fourier Transform technique and the method of multiple reference frames are employed to obtain the constant-speed performance of I.M. easily.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.627-628
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• 2010

S. Chow proposes white-box cryptography mechanism of AES algorithm(WBC-AES) in 2002. WBC mechanism is implementation method which is resistant to white-box attack. We describe the WBC-AES and contents protection method using it.

• Current Optics and Photonics
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• v.7 no.1
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• pp.54-64
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• 2023

This paper proposes dynamic viewing-zone switching for a binocular holographic three-dimensional display with low interpupil crosstalk and an extended eye-motion box. The optimal pupil geometry for reducing interpupil crosstalk is designed. It is shown that the eye-motion box can be extended by exploiting signal replication in the higher-order viewing zone. Design principles and numerical simulations for verification of the binocular holographic head-up display are presented.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.307-311
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• 2004

This paper presents an efficient architecture that optimizes the design of SEED S-box using composite field arithmetic. SEED is the Korean standard 128-bit block cipher algorithm developed by Korea Information Security Agency. The nonlinear function S-box is the most costly operation in terms. of size and power consumption, taking up more than 30% of the entire SEED circuit. Therefore the S-box design can become a crucial factor when implemented in systems where resources are limited such as smart cards. In this paper, we transform elements in $GF(2^8)$ to composite field $GF(((2^2)^2)^2)$ where more efficient computations can be implemented and transform the computed result back to $GF(2^8)$. This technique reduces the S-box portion to 15% and the entire SEED algorithm can be implemented at 8,700 gates using Samsung smart card CMOS technology.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2019.06a
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• pp.80-81
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• 2019

본 논문에서는 자연스러운 장면 영상에서 임의의 방향성을 가진 텍스트를 검출하기 위한 기법을 제안한다. 텍스트 검출을 위한 기본적인 프레임 워크는 Faster R-CNN[1]을 기반으로 한다. 먼저 RPN(Region Proposal Network)을 통해 다른 방향성을 가진 텍스트를 포함하는 bounding box를 생성한다. 이어서 RPN에서 생성한 각각의 bounding box에 대해 세 가지의 서로 다른 크기로 pooling된 특징지도를 추출하고 병합한다. 병합한 특징지도에서 텍스트와 텍스트가 아닌 대상에 대한 score, 정렬된 bounding box 좌표, 기울어진 bounding box 좌표를 모두 예측한다. 마지막으로 NMS(Non-Maximum Suppression)을 이용하여 검출 결과를 획득한다. COCO Text 2017 dataset[2]을 이용하여 학습 및 테스트를 진행하였으며 주관적으로 평가한 결과 기울어진 텍스트에 적합하게 회전된 영역을 얻을 수 있음을 확인하였다.

• ETRI Journal
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• v.30 no.1
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• pp.170-172
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• 2008

A substitution box (S-box) plays a central role in cryptographic algorithms. In this paper, an efficient method for designing S-boxes based on chaotic maps is proposed. The proposed method is based on the mixing property of piecewise linear chaotic maps. The S-box so constructed has very low differential and linear approximation probabilities. The proposed S-box is more secure against differential and linear cryptanalysis compared to recently proposed chaotic S-boxes.

• Bulletin of the Korean Space Science Society
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• 1998.10a
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• pp.38-38
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• 1998

No Abstract.See Full-text

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.88-97
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• 1989

This paper proposes an efficient switch-box router which consists of two parts ; greedy poly-jog router and via minimizer. The greedy switch-box router of Luk, routes not only metal wires at horizontal tracks and poly-silicon wires at vertical tracks but also poly-siliocon wires ar horizontal tracks if necessary. The via minimizer reduces the number of vias and the wire length by fipping of each corner, parallel moving of wire segment, transformation metal into poly-silicon, and transformation poly-silicon into metal. The result is generated through the column-wise scan across the routing region. The expected time complexity is O(M(Nnet)). Where M, N, and Nnet are respectively the number of columns, rows, and nets in the routing region.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.67-74
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• 2008

A compact and high-performance AES(Advanced Encryption Standard) encryption/decryption processor is designed by applying various hardware sharing and optimization techniques. In order to achieve minimized hardware complexity, sharing the S-Boxes for round transformation with the key scheduler, as well as merging and reusing datapaths for encryption and decryption are utilized, thus the area of S-Boxes is reduced by 25%. Also, the S-Boxes which require the largest hardware in AES processor is designed by applying composite field arithmetic on $GF(((2^2)^2)^2)$, thus it further reduces the area of S-Boxes when compared to the design based on $GF(2^8)$ or $GF((2^4)^2)$. By optimizing the operation of the 64-bit round transformation and round key scheduling, the round transformation is processed in 3 clock cycles and an encryption of 128-bit data block is performed in 31 clock cycles. The designed AES processor has about 15,870 gates, and the estimated throughput is 412.9 Mbps at 100 MHz clock frequency.