• 제목/요약/키워드: electronic atlas

검색결과 56건 처리시간 0.024초

Plasma Etch Damage가 (100) SOI에 미치는 영향의 C-V 특성 분석 (C-V Characterization of Plasma Etch-damage Effect on (100) SOI)

  • 조영득;김지홍;조대형;문병무;조원주;정홍배;구상모
    • 한국전기전자재료학회논문지
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    • 제21권8호
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    • pp.711-714
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    • 2008
  • Metal-oxide-semiconductor (MOS) capacitors were fabricated to investigate the plasma damage caused by reactive ion etching (RIE) on (100) oriented silicon-on-insulator (SOI) substrates. The thickness of the top-gate oxide, SOI, and buried oxide layers were 10 nm, 50 nm, and 100 nm, respectively. The MOS/SOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching. The measured C-V curves were compared to the numerical results from corresponding 2-dimensional (2-D) structures by using a Silvaco Atlas simulator.

4H-SiC Recessed-gate MESFET의 DC특성 모델링 연구 (Study on DC Analysis of 4H-SiC Recessed-Gate MESFETs using modeling tools)

  • 박승욱;강수창;박재영;신무환
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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    • pp.238-242
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    • 2001
  • In this paper, the current-voltage characteristics of a 4H-SiC MESFET is simulated by using the Atlas Simulation tool. we are able to use the simulator to extract more information about the new material 4H-SiC, including the mobility, velocity-field Curve and the Schottky barrier height. We have enabled and used the new simulator to investigate breakdown Voltage and thus predict operation limitiations of 4H-SiC device. Modeling results indicate that the Breakdown Voltage is 197 V and Current is 100 mA

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4H-SiC Recessed-gate MESFET의 DC특성 모델링 연구 (Study on DC Analysis of 4H-SiC Recessed-Gate MESFETs using modeling tooths)

  • 박승욱;강수창;박재영;신무환
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 추계학술대회 논문집
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    • pp.238-242
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    • 2001
  • In this paper, the current-voltage characteristics of a 4H-SiC MESFET is simulated by using the Atlas Simulation tool. we are able to use the simulator to extract more information about the new material 4H-SiC, including the mobility, velocity-field Curve and the Schottky barrier height. We have enabled and used the new simulator to investigate breakdown Voltage and thus predict operation limitations of 4H-SiC device. Modeling results indicate that the Breakdown Voltage is 197 V and Current is 100 mA

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Step doping 농도를 가지는 SOI RESURF LDMOSFET의 전기적 특성 분석 (Electrical characteristics of the SOI RESURF LDMOSFET with step doped epi-layer)

  • 김형우;서길수;김지홍;김남균
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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    • pp.361-364
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    • 2004
  • Surface doped SOI RESURF LDMOSFET with recessed source region is proposed to improve the on- and off-state characteristics. Surface region of the proposed LDMOS structure is doped like step. The characteristics of the proposed LDMOS is verified by two-dimensional process simulator ATHENA and device simulator ATLAS[1]. The numerically calculated on-resistance($R_{ON}$) of the proposed LDMOS is $10.36\Omega-cm$ and breakdown voltage is 205V when $L_{dr}=7{\mu}m$ with step doped surface.

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Thyristor 소자의 스트레스에 따른 소자파괴 메커니즘 연구 (Investigation of the thyristor failure mechanism induced by stress)

  • 김형우;서길수;김상철;강인호;김남균;김은동
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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    • pp.129-130
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    • 2005
  • The electrical stress has a major effect on the long-term reliability of the thyristor. Therefore, it is needed to analyze the relationship between reliability and stress. In this paper, we investigate the device failure mechanism which induced by the stress. And also investigate the effect of the thermal stress on the device failure and relationship between electrical and thermal stress. Two-dimensional process simulator ATHENA and device simulator ATLAS are used to analyze the failure mechanism of the device.

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Current Spreading Layer와 에피 영역 도핑 농도에 따른 4H-SiC Vertical MOSFET 항복 전압 최적화 (Optimization of 4H-SiC Vertical MOSFET by Current Spreading Layer and Doping Level of Epilayer)

  • 안정준;문경숙;구상모
    • 한국전기전자재료학회논문지
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    • 제23권10호
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    • pp.767-770
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    • 2010
  • In this work, we investigated the static characteristics of 4H-SiC vertical metal-oxidesemiconductor field effect transistors (VMOSFETs) by adjusting the doping level of n-epilayer and the effect of a current spreading layer (CSL), which was inserted below the p-base region with highly doped n+ state ($5{\times}10^{17}cm^{-3}$). The structure of SiC VMOSFET was designed by using a 2-dimensional device simulator (ATLAS, Silvaco Inc.). By varying the n-epilayer doping concentration from $1{\times}10^{16}cm^{-3}$ to $1{\times}10^{17}cm^{-3}$, we investigated the static characteristics of SiC VMOSFETs such as blocking voltages and on-resistances. We found that CSL helps distribute the electron flow more uniformly, minimizing current crowding at the top of the drift region and reducing the drift layer resistance. For that reason, silicon carbide VMOSFET structures of highly intensified blocking voltages with good figures of merit can be achieved by adjusting CSL and doping level of n-epilayer.

후열 처리에 따른 Ga2O3/4H-SiC 이종접합 다이오드 특성 분석 (Characteristics of Ga2O3/4H-SiC Heterojunction Diode with Annealing Process)

  • 이영재;구상모
    • 한국전기전자재료학회논문지
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    • 제33권2호
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    • pp.155-160
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    • 2020
  • Ga2O3/n-type 4H-SiC heterojunction diodes were fabricated by RF magnetron sputtering. The optical properties of Ga2O3 and electrical properties of diodes were investigated. I-V characteristics were compared with simulation data from the Atlas software. The band gap of Ga2O3 was changed from 5.01 eV to 4.88 eV through oxygen annealing. The doping concentration of Ga2O3 was extracted from C-V characteristics. The annealed oxygen exhibited twice higher doping concentration. The annealed diodes showed improved turn-on voltage (0.99 V) and lower leakage current (3 pA). Furthermore, the oxygen-annealed diodes exhibited a temperature cross-point when temperature increased, and its ideality factor was lower than that of as-grown diodes.

Analytical Modeling and Simulation for Dual Metal Gate Stack Architecture (DMGSA) Cylindrical/Surrounded Gate MOSFET

  • Ghosh, Pujarini;Haldar, Subhasis;Gupta, R.S.;Gupta, Mridula
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제12권4호
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    • pp.458-466
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    • 2012
  • A Dual metal gate stack cylindrical/ surrounded gate MOSFET (DMGSA CGT/SGT MOSFET) has been proposed and an analytical model has been developed to examine the impact of this structure in suppressing short channel effects and in enhancing the device performance. It is demonstrated that incorporation of gate stack along with dual metal gate architecture results in improvement in short channel immunity. It is also examined that for DMGSA CGT/SGT the minimum surface potential in the channel reduces, resulting increase in electron velocity and thereby improving the carrier transport efficiency. Furthermore, the device has been analyzed at different bias point for both single material gate stack architecture (SMGSA) and dual material gate stack architecture (DMGSA) and found that DMGSA has superior characteristics as compared to SMGSA devices. The analytical results obtained from the proposed model agree well with the simulated results obtained from 3D ATLAS Device simulator.

CT Angiography 영상에서 대동맥 추출을 위한 혈관 분할 알고리즘 성능 평가 (Performance evaluation of vessel extraction algorithm applied to Aortic root segmentation in CT Angiography)

  • 김태형;황영상;신기영
    • 한국정보전자통신기술학회논문지
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    • 제9권2호
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    • pp.196-204
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    • 2016
  • 세계보건기구협회에의 통계에 따르면 심장 혈관 질환의 발병률이 가장 높은 것으로 알려져 있다. CTA영상을 사용하여 관상동맥 및 대동맥 질환을 치료 및 검사할 수 있다. 혈관을 3차원으로 복원하는 과정이 의사의 숙련도에 따라 결과가 상이하며 복원 시간이 길다는 단점이 있으며 이를 극복하고자 자동으로 정확한 혈관을 추출하는 연구들이 진행되어 왔다. 본 논문에서는 자동 및 반자동 분할 기법인 Region Competition, Geodesic Active Contour(GAC), Multi-atlas based segmentation, Active Shape Model(ASM) 알고리즘을 CTA영상에 적용하여 대동맥 기부를 추출하였으며 하우스도르프 거리, 볼륨, 영상처리속도, 사용자 관여 여부, 그리고 관상동맥 심문 검출률을 비교 및 분석하였다. 추출된 3차원 대동맥 모델 중 가장 높은 정확도를 나타낸 알고리즘은 GAC인 반면 사용자 관여가 가장 높았기 때문에 실제 시술에 적용하기 위해서는 자동 분할 알고리즘 개선이 필요하다

P형 우물 영역의 도핑 농도와 면적에 따른 4H-SiC 기반 DMOSFET 소자 구조의 최적화 (Optimization of 4H-SiC DMOSFETs by Adjustment of the Dimensions and Level of the p-base Region)

  • 안정준;방욱;김상철;김남균;정홍배;구상모
    • 한국전기전자재료학회논문지
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    • 제23권7호
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    • pp.513-516
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    • 2010
  • In this work, a study is presented of the static characteristics of 4H-SiC DMOSFETs obtained by adjustment of the p-base region. The structure of this MOSFET was designed by the use of a device simulator (ATLAS, Silvaco.). The static characteristics of SiC DMOSFETs such as the blocking voltages, threshold voltages, on-resistances, and figures of merit were obtained as a function of variations in p-base doping concentration from $1\;{\times}\;10^{17}\;cm^{-3}$ to $5\;{\times}\;10^{17}\;cm^{-3}$ and doping depth from $0.5\;{\mu}m$ to $1.0\;{\mu}m$. It was found that the doping concentration and the depth of P-base region have a close relation with the blocking and threshold voltages. For that reason, silicon carbide DMOSFET structures with highly intensified blocking voltages with good figures of merit can be achieved by adjustment of the p-base depth and doping concentration.