• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2015년도 춘계학술대회 논문집
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• pp.178-178
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• 2015

SAP 씨앗층용 구리필름에 대한 결정구조와 에칭속도의 상관관계를 알아보았다. 그 결과, 저지수 면보다는 고지수면이 우선적으로 성장되어 있는 구리피막이 높은 에칭속도를 나타내었다. 이와 같은 우선결정방위와 에칭속도의 관계를 결정구조적인 관점에서 해석하였다.

• 한국재료학회지
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• 제11권11호
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• pp.923-928
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• 2001

An electrolytic silver plating process has been successfully developed for terminated electrode parts of dielectric ceramic resonator. High adhesion strength and high Qu is obtained and blister occurance is minimized under plating condition with $HNO_3$750 $m\ell/\ell$ and HF $ 250m\ell/\ell$ solution at $25^{\circ}C$ for 20 minutes. Adhesion strength has the highest value, 3.2 kg/mm$^2$ at etching temperature of $25^{\circ}C$. Adhesion strength, Qu and blister occurance are monotonically increased with the thickness of electrodeposition layer. In case of electrodeposition of Ag, Qu value of 380 has obtained higher than in case of electrolytic Cu plating with Qu value of 325. Therefore, terminated electrode parts of dielectric ceramic resonator reducing dielectric loss can be obtained using prensent process.

• 한국재료학회지
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• 제21권2호
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• pp.115-119
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• 2011

Si Nanowire (NW) field effect transistors (FETs) were fabricated on hard Si and flexible polyimide (PI) substrates, and their electrical characteristics were compared. Si NWs used as channels were synthesized by electroless etching method at low temperature, and these NWs were refined using a centrifugation method to get the NWs to have an optimal diameter and length for FETs. The gate insulator was poly(4-vinylphenol) (PVP), prepared using a spin-coating method on the PI substrate. Gold was used as electrodes whose gap was 8 ${\mu}m$. These gold electrodes were deposited using a thermal evaporator. Current-voltage (I-V) characteristics of the device were measured using a semiconductor analyzer, HP-4145B. The electrical properties of the device were characterized through hole mobility, $I_{on}/I_{off}$ ratio and threshold voltage. The results showed that the electrical properties of the TFTs on PVP were similar to those of TFTs on $SiO_2$. The bending durability of SiNWs TFTs on PI substrate was also studied with increasing bending times. The results showed that the electrical properties were maintained until the sample was folded about 500 times. But, after more than 1000 bending tests, drain current showed a rapid decrease due to the defects caused by the roughness of the surface of the Si NWs and mismatches of the Si NWs with electrodes.

• 멤브레인
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• 제13권1호
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• pp.9-19
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• 2003

무전해 PCB 도금 공정 수세액을 분리막으로 처리하여 투과수는 공업용수로 재사용하고 유가금속인 금(Au)을 회수하는 방법에 관하여 연구하였다. 역삼투 분리막 테스트 셀을 이용하여 수세액 처리에 적합한 분리막을 선정하였으며 scale-up을 위한 나권형 모듈 투과 실험을 실시하였다. 먼저, (주)새한에서 생산되는 RO-TL(tap water, low pressure), RO-BL(brackish water, low pressure), RO-normal(for water purifier)막으로 투과실험하였으며 그 중 RO-TL막이 soft etching, 촉매 및 Ni 수세액 처리에 우수한 것으로 판명되었다. 따라서 RO-TL막으로 제작한 나권형 가정용 정수기 모듈로 7bar, $25^{\circ}C$에서 scale-up 실험을 수행하였다. Au수세액의 투과 유속은 약 30 LMH로서 가장 높았으나 Au 제거율이 80% 미만이었다. Pd, Ni 및 soft etching 수세액의 투과유속은 각각 약 22, 17, 10 LMH 정도이며 Pd의 제거율은 85% 이상, Ni 및 Cu 제거율은 97% 이상이었다. 또한 Au, Ni 및 Cu 이온이 함유된 수세액 중 유가금속인 Au를 선택적으로 회수하기 위하여 NF막을 사용하였다. Au수세액 중 Ni 및 Cu 이온은 대부분 제거되었으며 투과액 중에 Au이온이 81.9% 존재하였고 계속하여 RO-TL막으로 Au를 농축 회수하였다. 마지막으로 4"직경의 NF 및 RO-TL 나권형 모듈을 연속적으로 사용하여 Au를 효과적으로 회수할 수 있음을 재확인하였다.인하였다.

• 한국재료학회지
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• 제20권1호
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• pp.25-30
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• 2010

Si nanowire/multiwalled carbon nanotube nanocomposite arrays were synthesized. Vertically aligned Si nanowire arrays were fabricated by Ag nanodendrite-assisted wet chemical etching of n-type wafers using $HF/AgNO_3$ solution. The composite structure was synthesized by formation of a sheath of carbon multilayers on a Si nanowire template surface through a thermal CVD process under various conditions. The results of Raman spectroscopy, scanning electron microscopy, and high resolution transmission electron microcopy demonstrate that the obtained nanocomposite has a Si nanowire core/carbon nanotube shell structure. The remarkable feature of the proposed method is that the vertically aligned Si nanowire was encapsulated with a multiwalled carbon nanotube without metal catalysts, which is important for nanodevice fabrication. It can be expected that the introduction of Si nanowires into multiwalled carbon nanotubes may significantly alter their electronic and mechanical properties, and may even result in some unexpected material properties. The proposed method possesses great potential for fabricating other semiconductor/CNT nanocomposites.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2012년도 춘계학술발표대회
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• pp.88.1-88.1
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• 2012

Silicon nanowires (SiNWs), due to their unusual quantum-confinement effects that lead to superior electrical and optical properties compared to those of the bulk silicon, have been widely researched as a potential building block in a variety of novel electronic devices. The conventional means for the synthesis of SiNWs has been the vapor-liquid-solid method using chemical vapor deposition; however, this method is time consuming, environmentally unfriendly, and do not support vertical growth. As an alternate, the electroless etching method has been proposed, which uses metal catalysts contained in aqueous hydrofluoric acids (HF) for vertically etching the bulk silicon substrate. This new method can support large-area growth in a short time, and vertically aligned SiNWs with high aspect ratio can be readily synthesized with excellent reproducibility. Nonetheless, there still are rooms for improvement such as the poor surface characteristics that lead to degradation in electrical performance, and non-uniformity of the diameter and shapes of the synthesized SiNWs. Here, we report a facile method of SiNWs synthesis having uniform sizes, diameters, and shapes, which may be other than just cylindrical shapes using a modified nanosphere lithography technique. The diameters of the polystyrene nanospheres can be adjustable through varying the time of O2 plasma treatment, which serve as a mask template for metal deposition on a silicon substrate. After the removal of the nanospheres, SiNWs having the exact same shape as the mask are synthesized using wet etching technique in a solution of HF, hydrogen peroxide, and deionized water. Different electrical and optical characteristics were obtained according to the shapes and sizes of the SiNWs, which implies that they can serve specific purposes according to their types.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 추계학술발표대회
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• pp.22.2-22.2
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• 2011

Si 나노와이어를 합성하는 다양한 방법들 중에서 Si 기판을 나노와이어 형태로 제작하는 무전해 식각법은 쉽고 간단하기 때문에 최근 많은 연구가 진행되고 있다. 무전해 식각법을 이용한 Si 나노와이어는 p 또는 n형의 전기적 특성을 갖는 Si 기판의 도핑농도에 따라 원하는 전기적 특성을 갖는 나노와이어를 얻을 수 있을 것이라는 기대가 있었지만 n형으로 제작된 나노와이어의 경우 식각에 의한 표면의 거칠기 때문에 그 특성을 나타내지 못하는 문제점을 가지고 있다. 본 연구에서는 무전해 식각법을 이용하여 p와 n형 나노와이어를 합성하고 field-effect transistors (FETs) 소자를 제작하여 각각의 특성을 구현하였다. 나노와이어와 절연막 사이의 계면 결함을 최소화하기 위하여 poly-4-vinylphenol (PVP) 고분자 절연막에 나노와이어를 삽입시킨 형태로 소자를 제작하였고, 특히 n형 나노와이어의 표면을 보다 평평하게 하기 위하여 열처리를 진행 하였다. 이렇게 각각의 특성이 구현된 나노와이어를 이용하여 soft-lithography 공정을 통해 complementary metal-oxide semiconductor (CMOS) 구조의 인버터 소자를 제작하였으며 그 전기적 특성을 평가하였다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2012년도 춘계학술발표대회
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• pp.79.1-79.1
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• 2012

Si 기판을 무전해 식각하여 나노와이어 형태로 합성하는 방법은 쉽고 간단하기 때문에 이를 이용한 소자 특성 연구가 많이 진행되고 있다. 하지만 이러한 방법으로 제작된 Si 나노와이어의 경우 식각에 의하여 나노와이어 표면이 매우 거칠어지기 때문에 고유의 특성을 나타내기 어려워 표면 특성을 제어 할 수 있는 연구의 필요성이 대두되고 있다. 본 연구에서는 무전해 식각법을 이용하여 p와 n형 나노와이어를 각각 합성하고 그 특성을 구현하기 위하여 표면조절을 진행하였다. 특히 n형 나노와이어의 경우 표면의 OH- 이온으로 인하여 n채널 특성이 제대로 나타나지 않기 때문에 열처리를 이용하여 표면을 보다 평평한 형태로 조절하여 향상된 전기적 특성을 얻을 수 있었다. 여기에 나노와이어와 절연막 사이의 계면 결함을 최소화 하기 위하여 poly-4-vinylphenol (PVP) 고분자 절연막에 나노와이어를 삽입시켜 나노와이어의 문턱전압 값을 조절하였다. 이를 바탕으로 complementary metal-oxide semiconductor(CMOS) 구조의 인버터 소자를 제작하였으며 p형 나노와이어가 절연막에 삽입된 정도에 따라 인버터의 midpoint voltage 값을 조절 할 수 있었다.

• 반도체디스플레이기술학회지
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• 제16권1호
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• pp.65-69
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• 2017

This paper presents a Technology-CAD (TCAD) simulation of the characteristics of crystalline Si pillar array solar cells. The junction depth and the surface concentration of the solar cells were optimized to obtain the targeted sheet resistance of the emitter region. The diffusion model was determined by calibrating the emitter doping profile of the microscale silicon pillars. The dimension parameters determining the pillar shape, such as width, height, and spacing were varied within a simulation window from ${\sim}2{\mu}m$ to $5{\mu}m$. The simulation showed that increasing pillar width (or diameter) and spacing resulted in the decrease of current density due to surface area loss, light trapping loss, and high reflectance. Although increasing pillar height might improve the chances of light trapping, the recombination loss due to the increase in the carrier's transfer length canceled out the positive effect to the photo-generation component of the current. The silicon pillars were experimentally formed by photoresist patterning and electroless etching. The laboratory results of a fabricated Si pillar solar cell showed the efficiency and the fill factor to be close to the simulation results.

• 한국표면공학회지
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• 제29권5호
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• pp.314-324
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• 1996

Scanning probe microscopes (SPMs) such as the scanning tunneling microscope (STM) and the atomic force microscope (AFM) were used for surface modification tools at the nanometer scale. Material surfaces, i. e., titanium, hydrogen-terminated silicon and trimethylsilyl organosilane monolayer on silicon, were locally oxidized with the best lateral spatial resolution of 20nm. The principle behind this proximal probe oxidation method is scanning probe anodization, that is, the SPM tip-sample junction connected through a water column acting as a minute electrochemical cell. An SPM-nanolithogrphy process was demonstrated using the organosilane monolayer as a resist. Area-selective chemical modifications, i. e., etching, electroless plating with gold, monolayer deposition and immobilization of latex nanoparticles; were achieved in nano-scale resolution. The area-selectivity was based on the differences in chemical properties between the SPM-modified and unmodified regions.