• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.63-70
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• 2016

To increase throughput efficiency and improve performance, FTN(Faster Than Nyquist) method and LDPC(Low Density Parity Code) codes are employed in DVB-S3 system. In this paper, we proposed efficient turbo equalization model to minimize inter symbol interference induced by FTN transmission. This paper introduces two conventional scheme employing SIC(Successive Interference Cancellation) and BCJR equalizer. Then, we proposed new scheme to resolve problems in this two conventional scheme. To make performance improved in turbo equalization model, the outputs of LDPC and BCJR equalizer are iteratively exchange probabilistic information. In fed LDPC outputs as extrinsic informa tion of BCJR equalizer. we split LDPC output to separate bit probabilities. We compare performance of proposed scheme to that of conventional methods through using simulation in AWGN(Additive White Gaussian Noise) channel. We confirmed that performance was improved compared to conventional methods as increasing throughput parameters of FTN.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.257-260
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm“Rijndael”. To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation the round transformation block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1323-1329
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• 2014

In this paper, we analyzed efficient decoding scheme with FTN (Faster than Nyquist) method that is transmission method faster than Nyquist theory and increase the throughput. we proposed viterbi equalizer model to minimize ISI (Inter-Symbol Interference) when FTN signal is transmitted. the proposed model utilized interference as branch information. In this paper, to decode FTN singal, we used turbo equalization algorithms that iteratively exchange probabilistic information between soft Viterbi equalizer (BCJR method) and LDPC decoder. By changing the trellis diagram in order to maximize Euclidean distance, we confirmed that performance was improved compared to conventional methods as increasing throughput of FTN signal.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.33-43
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.20-25
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• 2005

A high performance Viterbi decoder is designed using modified register exchange scheme and block decoding method. The elimination of the trace-back operation reduces the operation cycles to determine the merging state and the amount of memory. The Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoding methods in block decoding architectures. The elimination of trace-back also reduces the power consumption for finding the merging state and the access to the memory. The proposed decoder can be designed with emphasis on either efficient memory or low latency. Also, it has a scalable structure so that the complexity of the hardware and the throughput are adjusted by changing a few design parameters before synthesis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3A
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• pp.235-243
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• 2009

In this paper, we investigate the cognitive and cooperative communication scheme to improve the spectral efficiency in multiuser OFDMA systems using wireless relays. First, we propose the frame structure in which the efficient frequency reuse scheme with the cognitive technique is performed to increase the system throughput. And in the case where the THP (Tomlinson-Harashima preceding) is used for the elimination of interference from the relay, we derive the effective signal to noise ratio of the link largely affected by the channel quantization error. From the system level simulation results, it is shown that the proposed cognitive and cooperative communication scheme increases the overall system performance including the feedback overhead.

• Journal of Digital Convergence
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• v.17 no.9
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• pp.153-161
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• 2019

Discrimination of media object segments in wireless home proxies has a significant impact on caching delay, and caching delay degrades the performance of the proxy. In this paper, we propose a Single Fetching Smart Caching (SFSC) strategy and a Multi-Fetching Smart Caching (MFSC) strategy to improve the proxy performance of the home network and improve the caching performance for media object segments. The SFSC strategy is a technique that performs caching by sequential fetching of object segments requested by the home node one at a time, which guarantees a faster cache hit rate, and the MFSC strategy is a technique that caches the media object segments by blocking object segments requested by the home node one at a time, which improves the throughput of cache. Simulation results show that the cache hit rate and the caching delay are more efficient than the MFSC technique, and the throughput of the object segment is more efficient than that of the SFSC technique.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.5B
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• pp.539-548
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• 2011

We propose an efficient cooperative ARQ (Automatic Repeat reQuest) scheme for single-hop and multi-hop underwater acoustic communications, in which cooperative nodes are used to provide more reliable alternative paths for a specific source-to-destination connection. This alternative path has higher channel quality than that of the direct source-destination path. In addition, during a packet-relay through multiple hops, the typical acknowledgement (ACK) signal is replaced with overhearing data packet returned back from the next hop. The usage of overhearing as an ACK improves the system performance. In this paper, we evaluate the proposed scheme by comparing it with a conventional S&W ARQ in terms of throughput efficiency. Computer simulation results show that the proposed cooperative retransmission scheme can significantly improve the throughput by increasing the probability of successful retransmission.

• The Journal of the Korea Contents Association
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• v.5 no.3
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• pp.217-225
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• 2005

Currently the research on input-queued ATM switches is one of the most active research fields. Many achievements have been made in the research on scheduling algorithms for input-queued ATM switches and also applied in commerce. The scheduling algorithms have the characteristics of improving throughput, satisfying QoS requirements and providing service fairly. In this paper, we studied on an implementation of scheduler which arbitrates the input-queued ATM switches efficiently and swiftly. The proposed scheduler approximately provides $100\%$ throughput for scheduling. The proposed algorithm completes the arbitration for N-port VOQ switch with 4-iterative matching. Also the proposed algorithm has a merit for implementing the scheduling algorithm with 1/2 area compared to that of iSLIP scheduling algorithm which is widely used. The performance of the proposed scheduling algorithm is superior to that of iSLIP in 4-iterative matching.

• Journal of Communications and Networks
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• v.14 no.4
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• pp.434-442
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• 2012

Several gateway selection schemes have been proposed that select gateway nodes based on a single Quality of Service (QoS) path parameter, for instance path availability period, link capacity or end-to-end delay, etc. or on multiple non-QoS parameters, for instance the combination of gateway node speed, residual energy, and number of hops, for Mobile Ad hoc NETworks (MANETs). Each scheme just focuses on the ment of improve only a single network performance, i.e., network throughput, packet delivery ratio, end-to-end delay, or packet drop ratio. However, none of these schemes improves the overall network performance because they focus on a single QoS path parameter or on set of non-QoS parameters. To improve the overall network performance, it is necessary to select a gateway with stable path, a path with themaximum residual load capacity and the minimum latency. In this paper, we propose a gateway selection scheme that considers multiple QoS path parameters such as path availability period, available capacity and latency, to select a potential gateway node. We improve the path availability computation accuracy, we introduce a feedback system to updated path dynamics to the traffic source node and we propose an efficient method to propagate QoS parameters in our scheme. Computer simulations show that our gateway selection scheme improves throughput and packet delivery ratio with less per node energy consumption. It also improves the end-to-end delay compared to single QoS path parameter gateway selection schemes. In addition, we simulate the proposed scheme by considering weighting factors to gateway selection parameters and results show that the weighting factors improve the throughput and end-to-end delay compared to the conventional schemes.