• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.212-221
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• 1996

A CMOS comparator is designed for low voltage and low power operations. The proposed comparator consists of a preadmplifier followed by a regenerative latch. The preasmplifier reduces the power consumption to a half with the power-down mode and the dynamic offsets of the latch, which is affected by each device mismatch, is statistically analyzed. The circuit is designed and simulated using a 0.8.mu.m n-well CMOS process and the dissipated power is 0.16mW at a 20MHz clock speed based on a 3V supply.

• Journal of KIISE
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• v.42 no.12
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• pp.1623-1628
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• 2015

As the performance of mobile devices has increased, high-end multicore CPUs have become the norm in smartphones. However, such high performance devices are exposed to the problem of battery depletion due to the energy consumption caused by software performance, and despite increases in battery capacity. The required resources are dynamic and varied, and further user interaction is highly random; thus, Linux-based power management such as DVFS is needed to fulfill requirements. In order to reduce power consumption, we propose a method to restrict the CPU frequency of data download while maintaining user reactivity. This can supplement the weakness of existing Linux-based power management techniques like DVFS in relation to webpage loading. Through the implementation of our method at the application level, we confirm that energy consumption from webpage loading is reduced.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.143-146
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• 2011

A 50-MS/s 10-bit pipelined ADC with 1.2Vpp differential input range is proposed in this paper. The designed pipelined ADC consists of eight stage of 1.5bit/stage, one stage of 2bit/stage, digital error correction block, bias & reference driver, and clock generator. 1.5bit/stage is consists of sub-ADC, DAC and gain stage, Specially, a sample-and hold amplifier (SHA) is removed in the designed pipelined ADC to reduce the hardware and power consumption. Also, the proposed bootstrapped switch improves the Linearity of the input analog switch and the dynamic performance of the total ADC. The reference voltage was driven by using the on-chip reference driver without external reference. The proposed pipelined ADC was designed by using a 0.18um 1-poly 5-metal CMOS process with 1.8V supply. The total area including the power decoupling capacitor and power consumption are $0.95mm^2$ and 60mW, respectively. Also, the simulation result shows the ENOB of 9.3-bit at the Nyquist sampling rate.

• Architectural research
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• v.17 no.3
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• pp.109-115
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• 2015

The dynamic pricing of electricity, where the electricity rate increases in a time zone with a high demand for electricity is typically applied to a building whose power reception capacity is greater than a certain size. This includes the time of use(TOU) electricity pricing in Korea which can induce the effect of reducing the power demand of a building. Meanwhile, a VRF (Variable Refrigerant Flow) system that uses electricity is regarded as one of the typical heating and cooling systems along with central air conditioning (central HVAC) for its easy operation and application to the building. Thus, to reduce power energy and operating costs of a building in which the TOU and VRF systems are applied simultaneously, we suggested a control for changing the indoor temperature setting within the thermal comfort range or limiting the rotational speed of an inverter compressor. In this study, to describe the features of the above-mentioned control and verify its effects, we evaluated the results obtained from the analysis of its operation data. Through the actual measurements in winter operations for 73 days since mid- December 2014, we confirmed a reduction of 10.9% in power energy consumption and 12.2% in operating costs by the new control. Also, a reduction of 13.3% in power energy consumption was identified through a regression analysis.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.67 no.4
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• pp.208-213
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• 2018

In this paper, we studied the control strategy of applying STATCOM(static synchronous compensator) to mitigate the FIDVR(fault induced delayed voltage recovery) phenomenon. The proportion of motor loads is gradually increasing which might affect power system stability. Excessive reactive power consumption by the stall of the motor loads causes FIDVR phenomenon. In addition, the low inertia of the small HVAC(heating, ventilation and air conditioner) unit will not separate itself in the event of a contingency, causing system instability. For this reason, we have developed a control strategy that utilizes STATCOM efficiently through static and dynamic analysis. Case studies on a Korean power system have validated the performance of the proposed scheme under severe contingency scenarios. The results have verified that the proposed strategy can effectively mitigate FIDVR and improve the stability and reliability of the system.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.2
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• pp.312-334
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• 2023

In large-scale computing, cloud computing plays an important role by sharing globally-distributed resources. The evolution of cloud has taken place in the development of data centers and numerous servers across the globe. But the cloud information centers incur huge operational costs, consume high electricity and emit tons of dioxides. It is possible for the cloud suppliers to leverage their resources and decrease the consumption of energy through various methods such as dynamic consolidation of Virtual Machines (VMs), by keeping idle nodes in sleep mode and mistreatment of live migration. But the performance may get affected in case of harsh consolidation of VMs. So, it is a desired trait to have associate degree energy-performance exchange without compromising the quality of service while at the same time reducing the power consumption. This research article details a number of novel algorithms that dynamically consolidate the VMs in cloud information centers. The primary objective of the study is to leverage the computing resources to its best and reduce the energy consumption way behind the Service Level Agreement (SLA)drawbacks relevant to CPU load, RAM capacity and information measure. The proposed VM consolidation Algorithm (PVMCA) is contained of four algorithms: over loaded host detection algorithm, VM selection algorithm, VM placement algorithm, and under loading host detection algorithm. PVMCA is dynamic because it uses dynamic thresholds instead of static thresholds values, which makes it suggestion for real, unpredictable workloads common in cloud data centers. Also, the Algorithms are adaptive because it inevitably adjusts its behavior based on the studies of historical data of host resource utilization for any application with diverse workload patterns. Finally, the proposed algorithm is online because the algorithms are achieved run time and make an action in response to each request. The proposed algorithms' efficiency was validated through different simulations of extensive nature. The output analysis depicts the projected algorithms scaled back the energy consumption up to some considerable level besides ensuring proper SLA. On the basis of the project algorithms, the energy consumption got reduced by 22% while there was an improvement observed in SLA up to 80% compared to other benchmark algorithms.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.10
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• pp.5149-5167
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• 2017

Reducing energy consumption in a wireless video sensor network (WVSN) is a crucial problem because of the high video data volume and severe energy constraints of battery-powered WVSN nodes. In this paper, we present an adaptive dynamic resizing approach for a SRAM communication buffer in a WVSN node in order to reduce the energy consumption and thereby, to maximize the lifetime of the WVSN nodes. To reduce the power consumption of the communication part, which is typically the most energy-consuming component in the WVSN nodes, the radio needs to remain turned off during the data buffer-filling period as well as idle period. As the radio ON/OFF transition incurs extra energy consumption, we need to reduce the ON/OFF transition frequency, which requires a large-sized buffer. However, a large-sized SRAM buffer results in more energy consumption because SRAM power consumption is proportional to the memory size. We can dynamically adjust any active buffer memory size by utilizing a power-gating technique to reflect the optimal control on the buffer size. This paper aims at finding the optimal buffer size, based on the trade-off between the respective energy consumption ratios of the communication buffer and the radio part, respectively. We derive a formula showing the relationship between control variables, including active buffer size and total energy consumption, to mathematically determine the optimal buffer size for any given conditions to minimize total energy consumption. Simulation results show that the overall energy reduction, using our approach, is up to 40.48% (26.96% on average) compared to the conventional wireless communication scheme. In addition, the lifetime of the WVSN node has been extended by 22.17% on average, compared to the existing approaches.

• ETRI Journal
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• v.44 no.5
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• pp.849-858
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• 2022

Dynamic voltage frequency scaling (DVFS) has been widely adopted for runtime power management of various processing units. In the case of neural processing units (NPUs), power management of neural network applications is required to adjust the frequency and voltage every layer to consider the power behavior and performance of each layer. Unfortunately, DVFS is inappropriate for layer-wise run-time power management of NPUs due to the long latency of voltage scaling compared with each layer execution time. Because the frequency scaling is fast enough to keep up with each layer, we propose a layerwise dynamic frequency scaling (DFS) technique for an NPU. Our proposed DFS exploits the highest frequency under the power limit of an NPU for each layer. To determine the highest allowable frequency, we build a power model to predict the power consumption of an NPU based on a real measurement on the fabricated NPU. Our evaluation results show that our proposed DFS improves frame per second (FPS) by 33% and saves energy by 14% on average, compared with DVFS.

• Journal of Korea Society of Industrial Information Systems
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• v.17 no.4
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• pp.17-23
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• 2012

Ultra low-power design and energy harvesting applications require digital systems to operate under extremely low voltages approaching the point of balance between dynamic and static power consumption which is attained in the sub-threshold operation mode. Delay variations are extremely large in this mode. Therefore, in this paper, a new low-power logic design methodology using asynchronous NCL circuits is proposed to reduce power consumption and not to be affected by various technology variations in nanoscale MOSFET technology. The proposed NCL is evaluated using various benchmark circuits at 0.4V supply voltage, which are designed using 45nm MOSFET predictive technology model. The simulation results are compared to those of conventional synchrouns logic circuits in terms of power consumption and speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.