• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.1-8
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• 2013

TIn this paper, we propose a high performance L1 cache structure on the high clock CPU of 4GHz. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to exploit temporal locality, and a buffer-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is selectively stored into the two-way set associative buffer. For the high performance and low power consumption, we propose an one way among two ways set associative buffer is selectively accessed based on the buffer-select table(BST). According to simulation results, Energy $^*$ Delay product can improve about 45%, 70% and 75% compared with a direct mapped cache, a four-way set associative cache, and a victim cache with two times more space respectively.

• ETRI Journal
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• v.24 no.5
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• pp.360-372
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• 2002

In this paper, we propose the modified dynamic weighted round robin (MDWRR) cell scheduling algorithm, which guarantees the delay property of real-time traffic and also efficiently transmits non-real-time traffic. The proposed scheduling algorithm is a variation of the dynamic weighted round robin (DWRR) algorithm and guarantees the delay property of real-time traffic by adding a cell transmission procedure based on delay priority. It also uses a threshold to prevent the cell loss of non-real-time traffic that is due to the cell transmission procedure based on delay priority. Though the MDWRR scheduling algorithm may be more complex than the conventional DWRR scheme, considering delay priority minimizes cell delay and decreases the required size of the temporary buffer. The results of our performance study show that the proposed scheduling algorithm has better performance than the conventional DWRR scheme because of the delay guarantee of real-time traffic.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.17 no.2
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• pp.103-113
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• 2013

We analyze the queueing model for leaky bucket (LB) scheme with dynamic arrivals and token rates. In other words, in our LB scheme the arrivals and token rates are changed according to the buffer occupancy. In telecommunication networks, the LB scheme has been used as a policing function to prevent congestion. By considering bursty and correlated properties of input traffic, the arrivals are assumed to follow a Markov-modulated Poisson process (MMPP). We derive the distribution of system state, and obtain the loss probability and the mean waiting time. The analysis is done by using the embedded Markov chain and supplementary variable method. We also present some numerical examples to show the effect of our proposed model.

• The KIPS Transactions:PartC
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• v.8C no.3
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• pp.287-298
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• 2001

본 논문에서는 ATM 기반 MPLS 망에서 효율적으로 IP 서비스를 전송하기 위한 동적 버퍼관리 방식의 Dynamic GSMP V3(General Switching Management Protocol Version 3)의 VLSI 구현을 위한 하드웨어 구조를 제안하고 설계하였다. 또한 현재 표준화중인 GSMP와 동적 버퍼관리 방식을 수용한 GSMP를 셀 손실률 측면에서 비교 분석하였다. ATM 스위치 상에 연결 제어의 성능 향상을 위해 스위치 상에 연결 제어의 성능 향상을 위해 스위치에서 연결설정 및 제어를 수행하는 Dynamic GSMP V3의 Slave 블록을 삼성 SoG 0.5$\mu\textrm{m}$ 공정으로 설계하였다. 기존의 방식과 제안한 방식의 성능 평가를 위해 확률 랜덤 변수에 의해 발생된 셀과 최소 버퍼 알고리즘을 이용하여 모의 실험을 하였으며, 이때 셀 손실률이 향상되었음을 알 수 있었다.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.5
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• pp.94-103
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• 1997

It is necesary that analog buffer circuit should drive an external load in the VLSI design such as switched capacitor efilter (SCF), D/A converter, A/d converter, telecommunicatin circuit, etc. The conventional CMOS buffer circuit have many probvlems according as CMOS technique. Firstly, Capacity of large load ar enot able to opeate well. The problem can be solve to use class AB stages. But large load are operated a difficult, because an element of existing CMOS has a quadratic functional relation with inptu and outut voltage versus output current. Secondly, whole circuit of dynamic rang edecrease, because a range of inpt and output voltages go down according as increasing of intergration rate drop supply voltage. In this paper suggests that new differential CMOS line driver make out of operating an external of large load. In telecommunication's chip case transmission line could be a load. It is necessary that a load operate line driver. The proposal circuit is planned to hav ea high generation power rnage of voltage with preservin linearity. And circuit of capability is inspected through simulation program (HSPICE).

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.413-417
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• 2009

The use of scalable video coding scheme has been regarded as a promising solution for guaranteeing the quality of service of the video streaming over the Internet because it is a capable coding scheme to perform quality adaptation depending on network conditions. In this paper, we use a streaming model that transmits base layer using TCP and enhancement layers using DCCP, which try to provide transmission reliability of the BL and TCP friendliness. Unlike pervious works, the proposed algorithm performs rate adaptation based on playout buffer status. The PoB status of the client is sent back periodically to the server and serves as a network congestion indicator. Experimental results show that our scheme improves streaming quality comparing with pervious scheme in the case of not only constant/dynamic background flows but also VBR-encoded video sequence.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.81-83
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• 1999

주문형 비디오 시스템에서 사용자 요청의 초기대기시간과 메모리 요구량을 줄이기 위해서는 각 사용자 요청에 할당되는 버퍼의 크기를 최소화하는 것이 필요하다. 이는 초기대기시간과 메모리 요구량이 사용자 요청에 할당되는 버퍼의 크기에 따라 지수적으로 증가하기 때문이다. 그러나 기존의 버퍼 할당 기법은 시스템이 완전 부하인 상태만을 고려하여 버퍼 크기를 결정하고 할당함으로써 필요이상의 큰 버퍼를 각 사용자 요청에 할당한다. 그래서 본 논문에서는 시스템의 실행시간 정보(runtime information)를 활용하여 버퍼크기를 결정하고 할당함으로써 불필요한 메모리 할당을 없애는 동적 버퍼 할당 기법을 제안한다. 동적 버퍼 할당 기법은 특정 버퍼 스케쥴링 방식에 의존된 것이 아니기 때문에 기존의 모든 버퍼 스케쥴링 방식에 적용이 가능하다. 본 논문에서는 성능 평가를 통해 동적 버퍼 할당 기법의 우수성을 보인다.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.65-65
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• 2000

For Video on Demand(VoD) servers, a design of an efficient scheduler is important to the support a large number of clients having various playback speeds and receiving rates. In this paper, we propose the scheduling algorithm to handle establishing deadlines and selection using the earliest deadline first. To establish deadlines and selections, the period of the receiving rates for each client is located between the over-max receiving rate and the over-playback rate. To avoid video starvation and the buffer overflow of each client, the proposed algorithm guarantees providing the admission control. Because of establishing deadlines and selection, period of each client receiving is between one over max receiving rate and one over play back rate. Using Virtual Buffer in server, scheduling load is reduced. The efficiency of the proposed algorithm is verified using a Petri Net_Based simulation tool, Exspect.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2454-2456
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• 2002

Since articuratory synthesis models the human vocal organs as precise as possible, it is potentially the most desirable method to produce various words and languages. This paper proposes a new type of an articulatory synthesizer using Mermelstein vocal tract model and Kelly-Lochbaum digital filter. Previous researches have assumed that the length of the vocal tract or the number of its cross sections dose not vary while uttering. However, the continuous utterance can not be easily implemented under this assumption. The limitation is overcomed by "Buffer Rearrangement" for dynamic vocal tract in this paper.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.61-67
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• 2020

This paper is to propose a hybrid memory adaptor using next-generation nonvolatile memory devices such as phase-change memory to improve the performance limitations of OpenStack-based object storage systems. The proposed system aims to improve the performance of the account and container servers for object metadata management. For this, the proposed system consists of locality-based dynamic page buffer, write buffer, and nonvolatile memory modules. Experimental results show that the proposed system improves the hit rate by 5.5% compared to the conventional system.