• Proceedings of the KIEE Conference
• /
• 2005.11b
• /
• pp.145-147
• /
• 2005

This paper presents a methodology for satisfying the thermal comfort of Indoor environment and reducing the summer peak demand power by minimizing the power consumption for an Air-conditioner within a space. KEPCO(Korea Electric Power Corporation) use the fixed duty cycle control method regardless of the indoor thermal environment. This method has disadvantages that energy saying depends on the set-point value of the Air-Conditioner and DLC has no net effects on Air-conditioners if the appliance has a lower operating cycle than the fixed duty cycle. A variable duty cycle estimates the PMV(Predict Mean Vote) at the next step with a predicted temperature and humidity coming from the back propagation neural network model. It is possible to reduce the energy consumption by maintaining the Air-conditioner's OFF state when the PMV lies in the thermal comfort range. The proposed methodology uses the historical real data of Sep. 7th, 2001 from a classroom in seoul to verify the effectiveness of the variable duty cycle method comparing with fixed duty cycle. The result shows that the variable duty cycle reduces the peak demand to 2.6times more than fixed duty cycle and increases the load control ratio by 8% more. Based on the variable duty cycle control algorithm, the effectiveness of DLC is much more improved as compared with the fixed duty cycle.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.3 no.4
• /
• pp.330-337
• /
• 1998

A duty cycle average model is mathematically developed for an average model of buck converter employing hysteresis c control. The derived model is able to simultaneously deal with both the continuous conduction mode (CCM) and the d discontinuous conduction mode (DCM) in the time domain. Also. taking advantage of the MAST language of SABER. a t template of the proposed duty cycle average model is built for the time and frequency domain analyses. The accuracy of t this template is verified through the computer simulations.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.28 no.2
• /
• pp.113-119
• /
• 2017

In this paper, we have shown the performance analysis results of the LoRa low power wide area network under duty cycle local regulation in Korean RFID/USN frequency band. Especially, we analyzed uplink throughput and data transmission time of a single LoRa end device. From the analysis results, duty cycle regulation, in which a data transmission should be ended within 0.4 second, limits the performance of LoRa network. Therefore, it is necessary to revise Korea's duty cycle regulation referencing EU regulation in order to assess LoRa network in Korea.

• Journal of Applied Reliability
• /
• v.11 no.4
• /
• pp.433-445
• /
• 2011

Duty cycle is determined as the ratio of operating time to total time. Duty cycle in reliability prediction is one of the significant factors to be considered. In duty cycle application, non-operating time failure rate has been easily ignored even though the failure rate in non-operating period has not been proved to be small enough. Ignorance of non-operating time failure rate can result in over-estimated system reliability calculation. Furthermore, utilization of duty cycle in reliability prediction has not been evaluated in its effectiveness. In order to address these problems, two reliability models, such as MIL-HDBK-217F and RIAC-HDBK-217Plus, were used to analyze non-operating time failure rate. This research has proved that applying duty cycle in 217F model is not reasonable by the quantitative comparison and analysis.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.2
• /
• pp.222-227
• /
• 2012

In this paper, we analyze the total performance according to duty cycle of interfering transmitter in hetero systems. We analyze this criteria as a parameter for co-use when hetero systems share the same frequency channels. In order to make an analysis of relationship between duty cycle and performances of two systems. We take into consideration on the case that WiBro is an victim receiver and WLAN is a interfering transmitter. Analyzed coexistence results may be widely applied into the technique developed to get the coexisting condition for wireless devices using many communication protocols in same frequency.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.10
• /
• pp.142-147
• /
• 2012

This paper presents a mixed-mode CMOS duty-cycle corrector (DCC) circuit that has a dynamic frequency scaling (DFS) counter and coarse and fine tuning adjustments. A higher duty-cycle correction accuracy and smaller jitter have been achieved by utilizing the DFS counter that reduces the bit-switching glitch effect of a digital to analog converter (DAC). The proposed circuit has been designed using a 0.18-${\mu}m$ CMOS process. The measured duty cycle error is less than ${\pm}1.1%$ for a wide input duty-cycle range of 25-75% over a wide freqeuncy range of 0.5-1.5 GHz.

• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.1
• /
• pp.39-43
• /
• 2013

The experiments were carried out in the variation of current density, pH, temperature, and duty cycle to investigate the influence of electroplating parameters on the properties of Ni-Fe invar alloys. When the current density and temperature were changed, the composition of invar alloy was varied, however, duty cycle and pH hardly affected on the composition of electrodeposited alloys. However, as the duty cycle was increased, microstructure was changed and the decrease of hardness was also observed.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.9 s.339
• /
• pp.29-34
• /
• 2005

This paper describes a novel internal clock generator, called duty cycle-corrected analog synchronous mirror delay (DCC-ASMD). The proposed circuit is well suited for dual edge-triggered systems such as double data-rate synchronous DRAM since it can achieve clock synchronization within two clock cycles with accurate duty cycle correction. To evaluate the performance of the proposed circuit, DCC-ASMD was designed using a $0.35\mu$m CMOS process technology. Simulation results show that the proposed circuit generates an internal clock having $50\%$ duty ratio within two clock cycles from the external clock having duty ratio range of $40\;\~\;60$.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.12 no.10
• /
• pp.4754-4773
• /
• 2018

In sensor medium access control (SMAC) protocol, sensor nodes can only access the channel in the scheduling and listening period. However, this fixed working method may generate data latency and high conflict. To solve those problems, scheduling duty in the original SMAC protocol is divided into multiple small scheduling duties (micro duty MD). By applying different micro-dispersed contention channel, sensor nodes can reduce the collision probability of the data and thereby save energy. Based on the given micro-duty, this paper presents an adaptive duty cycle (DC) and back-off algorithm, aiming at detecting the fixed duty cycle in SMAC protocol. According to the given buffer queue length, sensor nodes dynamically change the duty cycle. In the context of low duty cycle and low flow, fair binary exponential back-off (F-BEB) algorithm is applied to reduce data latency. In the context of high duty cycle and high flow, capture avoidance binary exponential back-off (CA-BEB) algorithm is used to further reduce the conflict probability for saving energy consumption. Based on the above two contexts, we propose an improved SMAC protocol, micro duty adaptive SMAC protocol (MDA-SMAC). Comparing the performance between MDA-SMAC protocol and SMAC protocol on the NS-2 simulation platform, the results show that, MDA-SMAC protocol performs better in terms of energy consumption, latency and effective throughput than SMAC protocol, especially in the condition of more crowded network traffic and more sensor nodes.

• Journal of the Semiconductor & Display Technology
• /
• v.14 no.1
• /
• pp.67-71
• /
• 2015

Pulse electroplating was studied to form nanocrystal structure effectively by changing plating current density and duty cycle. When both of plating current density and duty cycle were decreased from $100mA/cm^2$ and 70% to $50mA/cm^2$ and 30%, the P content in the Ni matrix was increased almost up to the composition of $Ni_3P$ compound and the grain growth after annealing was retarded as well. The as-plated hardness values ranging from 660 to 753 HV are mainly based on the formation of nanocrystal structure. On the other hand, the post-anneal hardness values ranging from 898 to 1045 HV, which are comparable to the hardness of hard Cr, are coming from how competition worked between the precipitation of $Ni_3P$ and the grain coarsening. According to the ANOVA and regression analysis, the plating current density showed more strong effect on nanocrystal size and film hardness than the duty cycle.