• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.145-150
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• 2013

This paper has presented the analysis for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET as next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function has been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold characteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering are changed, and the deviation rate is changed for device parameters for DGMOSFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.709-711
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• 2011

본 연구에서는 Double-gate MOSFET의 DIBL(Drain Induced Barrier Lowering)의 특성을 분석하기 위하여 분석학적 전송모델을 사용하였으며 분석학적 모델을 유도하기 위하여 포아송방정식을 풀 때 급수함수를 이용하였다. 단채널 효과에서는 유효채널길이 감소와 문턱전압 감소 그리고 DIBL이 있다. DIBL은 드레인 전압 변화에 따른 문턱전압의 변화로 알 수 있다. 채널길이가 감소하면 DIBL은 감소하지만, 채널길이가 감소하면 단채널 효과가 증가한다. 본 논문에서는 채널길이에 따른 DIBL을 분석하였고, 또한 채널 두께 및 게이트 산화막의 두께에 대한 DIBL에 대하여 분석하였다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.21-28
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• 1999

A new method of making high speed self-aligned ESD (Elevated Source/Drain) MOSFET is proposed. Different from the conventional LDD (Lightly-Doped Drain) structure, the proposed ESD structure needs only one ion implantation step for the source/drain junctions, and makes it possible to modify the depth of the recessed channel by use of dry etching process. This structure alleviates hot-carrier stress by use of removable nitride sidewall spacers. Furthermore, the inverted sidewall spacers are used as a self-aligning mask to solve the self-align problem. Simulation results show that the impact ionization rate ($I_{SUB}/I_{D}$) is reduced and DIBL (Drain Induced Barrier Lowering) characteristics are improved by proper design of the structure parameters such as channel depth and sidewall spacer width. In addition, the use of removable nitride sidewall spacers also enhances hot-carrier characteristics by reducing the peak lateral electric field in the channel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.799-804
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• 2016

To analyze the phenomenon of drain induced barrier lowering(DIBL) for top and bottom gate oxide thickness of asymmetric double gate MOSFET, the deviation of threshold voltage is investigated for drain voltage to have an effect on barrier height. The asymmetric double gate MOSFET has the characteristic to be able to fabricate differently top and bottom gate oxide thickness. DIBL is, therefore, analyzed for the change of top and bottom gate oxide thickness in this study, using the analytical potential distribution derived from Poisson equation. As a results, DIBL is greatly influenced by top and bottom gate oxide thickness. DIBL is linearly decreased in case top and bottom gate oxide thickness become smaller. The relation of channel length and DIBL is nonlinear. Top gate oxide thickness more influenced on DIBL than bottom gate oxide thickness in the case of high doping concentration in channel.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1357-1359
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• 2001

0.2${\mu}m$ 이하의 최소 선폭을 가지는 소자를 구현할 때 drain induced barrier lowering (DIBL)이나 hot electron effect와 같은 short channel effect (SCE)가 나타나며 이로 인하여 소자의 신뢰성이 악화되기도 한다. 이를 개선하기 위한 방법 중 하나가 silicon selective epitaxial growth (SEG)를 이용한 elevated source/drain (ESD) 구조이다. 본 연 구에서는 silicon selective epitaxial growth를 이용하여 elevated source/drain 구조를 갖는 MOSFET 소자와 일반적인 MOSFET 구조를 갖는 소자와의 차이를 elevated source/drain의 높이 변화에 따른 전류 전압 특성을 이용하여 비교, 분석하였으며 그 결과 elevated source/drain 구조가 short channel effect를 감소시킴을 확인할 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.1-7
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• 2006

3-dimensional(3-D) simulations of ideal double-gate bulk FinFET were performed extensively and the electrical characteristics. were analyzed. In 3-D device simulation, we changed gate length($L_g$), height($H_g$), and channel doping concentration($N_b$) to see the behaviors of the threshold voltage($V_{th}$), DIBL(drain induced barrier lowering), and SS(subthreshold swing) with source/drain junction depth($X_{jSDE}$). When the $H_g$ is changed from 30 nm to 45nm, the variation gives a little change in $V_{th}$(less than 20 mV). The DIBL and SS were degraded rapidly as the $X_{jSDE}$ is deeper than $H_g$ at low fin body doping($1{\times}10^{16}cm^{-3}{\sim}1{\times}10^{17}cm^{-3}$). By adopting local doping at ${\sim}10nm$ under the $H_g$, the degradation could be suppressed significantly. The local doping also alleviated $V_{th}$ lowering by the shallower $X_{jSDE}\;than\;H_g$ at low fin body doping.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.434-438
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• 2014

CMOS의 최종형태로써 Gate-All-Around(GAA) Silicon Nanowire(NW)가 각광받고 있다. 이 논문에서 NW FET(Field Effect Transistor)의 채널 길이와 NW의 폭과 같은 size에 따른 특성변화를 실제 실험 data와 NW FET 특성분석 simulation을 이용해서 비교해보았다. MOSFET(Metal Oxide Semiconductor Field Effect Transistor)의 소형화에 따른 쇼트 채널 효과(short channel effect)에 의한 threshold voltage($V_{th}$), Drain Induced Barrier Lowering(DIBL), subthreshold swing(SS) 또한 비교하였다. 이에 더하여, 기존의 상용툴로 NW를 해석한 시뮬레이션 결과와도 비교해봄으로써 NW의 size scaling에 대한 EDISON NW 해석 simulation의 정확도를 파악해보았다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.110-116
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• 2009

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.69-76
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• 2005

Interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are determined as $1.5{\times}10^{13} traps/cm^2$, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by $N_2$ annealing. Based on the diode characteristics, various sizes of erbium- silicided/platinum-silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20 m to 35nm. The manufactured SB-MOSFETs show excellent drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are compatible with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.1-7
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• 2004

We performed two-dimensional (20) computer-based modeling and simulation of FinFET by solving the coupled Poisson-Schrodinger equations quantum-mechanically in a self-consistent manner. The simulation results are carefully investigated for FinFET with gate length(Lg) varying from 10 to 80nm and with a Si-fin thickness($T_{fin}$) varying from 10 to 40nm. Current-voltage (I-V) characteristics are compared with the experimental data. Device optimization has been performed in order to suppress the short-channel effects (SCEs) including the sub-threshold swing, threshold voltage roll-off, drain induced barrier lowering (DIBL). The quantum-mechanical simulation is compared with the classical appmach in order to understand the influence of the electron confinement effect. Simulation results indicated that the FinFET is a promising structure to suppress the SCEs and the quantum-mechanical simulation is essential for applying nano-scale device structure.