• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.212-213
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• 2008

This paper describes the analysis of the device characteristics of the NPT type 1200V Insulated gate Bipolar Transistor. In case of NPT type IGBT devices, optimized n-epi layer thickness and concentration is important to obtain low on-state voltage and breakdown voltage characteristics. In this paper, we analyzed on-state and off-state characteristics of NPT type IGBT. Breakdown voltage of designed IGBT was higher than 1200V when we optimized Field Limiting Ring structures. And also, on-state voltage characteristics was shown less then 2.5V at 25A of drain current.

• ETRI Journal
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• v.16 no.4
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• pp.1-11
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• 1995

A GaAs power metal semiconductor field effect transistor (MESFET) operating at a voltage as low as 3.3V has been developed with the best performance for digital handheld phone. The device has been fabricated on an epitaxial layer with a low-high doped structure grown by molecular beam epitaxy. The MESFET, fabricated using $0.8{\mu}m$ design rule, showed a maximum drain current density of 330 mA/mm at $V_{gs}$ =0.5V and a gate-to-drain breakdown volt-age of 28 V. The MESFET tested at a 3.3 V drain bias and a 900 MHz operation frequency displayed an output power of 32.5-dBm and a power added efficiency of 68%. The associate power gain at 20 dBm input power and the linear gain were 12.5dB and 16.5dB, respectively. Two tone testing measured at 900.00MHz and 900.03MHz showed that a third-order intercept point is 49.5 dBm. The power MESFET developed in this work is expected to be useful as a power amplifying device for digital hand-held phone because the high linear gain can deliver a high power added efficiency in the linear operation region of output power and the high third-order intercept point can reduce the third-order intermodulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1069-1074
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• 2017

Reduction of breakdown voltage is serious short channel effect (SCE) by shrink of channel length. The deviation of breakdown voltage for doping concentration is investigated with structural parameters of sub-10 nm double gate (DG) MOSFET in this paper. To analyze this, thermionic and tunneling current are derived from analytical potential distribution, and breakdown voltage is defined as drain voltage when the sum of two currents is $10{\mu}A$. As a result, breakdown voltage increases with increase of doping concentration. Breakdown voltage decreases by reduction of channel length. In order to solve this problem, it is found that silicon and oxide thicknesses should be kept very small. In particular, as contributions of tunneling current increases, breakdown voltage increases.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.8-14
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• 2012

The device performances of n-channel MuGFET with different fin numbers and fin widths but the total effective channel width is constant have been characterized. Two kinds of Pi-gate devices with fin number=16, fin width=55nm, and fin number=14, fin width=80nm have been used in characterization. The threshold voltage, effective electron mobility, threshold voltage roll-off, inverse subthreshold slope, PBTI, hot carrier degradation, and drain breakdown voltage have been characterized. From the measured results, the short channel effects have been reduced for narrow fin width and large fin numbers. PBTI degradation was more significant in devices with large fin number and narrow fin width but hot carrier degradation was similar for both devices. The drain breakdown voltage was higher for devices with narrow fin width and large fin numbers. With considering the short channel effects and device degradation, the devices with narrow fin width and large fin numbers are desirable in the device layout of MuGFETs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.8-14
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• 2011

The optimal geometry of the gate field plate in AlGaN/GaN-on-Si HEMT has been proposed using two-dimensional device simulation to achieve a high breakdown voltage for a given gate-to-drain distance. It was found that the breakdown voltage was drastically enhanced due to the reduced electric field at the gate corner when a gate field plate was employed. The electric field distribution at the gate corner and the field plate edge was investigated as functions of field plate length and insulator thickness. According to the simulation results, the electric field at the gate corner can be successfully reduced even with the field plate length of 1 ${\mu}m$. On the other hand, when the field plate length is too long, the distance between field plate and drain electrode is reduced below a critical level, which eventually lowers the breakdown voltage. The highest breakdown voltage was achieved with the field plate length of 1 ${\mu}m$. According to the simulation results varying the $SiN_x$ film thickness for the fixed field plate length of 1 ${\mu}m$, the optimum thickness range of the $SiN_x$ film was 200 - 300 nm where the electric field strength at the field plate edge counterbalances that of the gate corner.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.176-176
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• 2003

The effects of oxide thickness and gate length of MgO/GaN metal oxide semiconductor field effect transistors (MOSFETs) on I-V, threshold voltage and breakdown voltage characteristics were examined using a drift-diffusion model. The saturation drain current scales in an inverse logarithmic fashion with MgO thickness and is < 10$^{-3}$ A.${\mu}{\textrm}{m}$$^{-1}$ for 0.5 ${\mu}{\textrm}{m}$ gate length devices with oxide thickness > 600 $\AA$ or for all 1 ${\mu}{\textrm}{m}$ gate length MOSFETs with oxide thickness in the range of >200 $\AA$. Gate breakdown voltage is > 100 V for gate length >0.5 ${\mu}{\textrm}{m}$ and MgO thickness > 600 $\AA$. The threshold voltage scales linearly with oxide thickness and is < 2 V for oxide thickness < 800 $\AA$ and gate lengths < 0.6 ${\mu}{\textrm}{m}$. The GaN MOSFET shows excellent potential for elevated temperature, high speed applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.9
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• pp.911-915
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• 2004

In this study, the electrical characteristics of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated depending on its process and design parameter. In order to verify the experimental data, two-dimensional device simulation was carried out simultaneously. The off- state breakdown voltages of n-channel LDMOSFETs were increased nearly in proportional to the drift region length. For the case of decreasing n-well ion implant doses from $1.0\times{10}^{13}/cm^2$ to $1.0\times{10}^{12}/cm^2$, the off-state breakdown voltage was increased approximately two times. The on-resistance was also increased about 76 %. From 2-D simulation, the increase in the breakdown voltage was attributed to a reduction in the maximum electric field of LDMOS imolanted with low dose as well as to a shift toward n+ drain region. Moreover, the on- and off-state breakdown voltages were also linearly increased with increasing the channel to n-tub spacing due to the reduction of impact ionization at the drift region. The experimental and design data of these high-voltage LDMOS devices can widely applied to design smart power ICs with low-voltage CMOS control and high-voltage driving circuits on the same chip.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.688-690
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• 2017

Reduction of breakdown voltage is serious short channel effect (SCE) by shrink of channel length. The SCE occurred in on-state transistor raises limitation of operation range of transistor. The deviation of breakdown voltage for doping concentration is investigated with structural parameters of sub-10 nm double gate (DG) MOSFET in this paper. To analyze this, thermionic and tunneling current are derived from analytical potential distribution, and breakdown voltage is defined as drain voltage when the sum of two currents is $10{\mu}A$. As a result, breakdown voltage increases with increase of doping concentration. Breakdown voltage decreases by reduction of channel length. In order to solve this problem, it is found that silicon and oxide thicknesses should be kept very small. In particular, as contributions of tunneling current increases, breakdown voltage increases.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.6
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• pp.41-50
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• 1995

A state-of-the-arts GaAs power metal semiconductor field effect transistor (MESFET) for 3.3V operation digital hand-held phone at 900 MHz has been developed for the first time, The FET was fabricated using a low-high doped structures grown by molecular beam epitaxy (MBE). The fabricated MESFETs with a gate width of 16 mm and a gate length of 0.8 .mu.m shows a saturated drain current (Idss) of 4.2A and a transconductance (Gm) of around 1700mS at a gate bias of -2.1V, corresponding to 10% Idss. The gate-to-drain breakdown voltage is measured to be 28 V. The rf characteristics of the MESFET tested at a drain bias of 3.3 V and a frequencyof 900 MHz are the output power of 32.3 dBm, the power added efficiency of 68%, and the third-ordr intercept point of 49.5 dBm. The power MESFET developed in this work is expected to be useful as a power amplifying device for digital hand-held phone because the high linear gain can deliver a high power added efficiency in the linear operation region of output power and the high third-order intercept point can reduce the third-order inter modulation.

• ETRI Journal
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• v.39 no.1
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• pp.62-68
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• 2017

In this paper, we present the design and characterization analysis of a cascode GaN field-effect transistor (FET) for switching power conversion systems. To enable normally-off operation, a cascode GaN FET employs a low breakdown voltage (BV) enhancement-mode Si metal-oxide-semiconductor FET and a high-BV depletion-mode (D-mode) GaN FET. This paper demonstrates a normally-on D-mode GaN FET with high power density and high switching frequency, and presents a theoretical analysis of a hybrid cascode GaN FET design. A TO-254 packaged FET provides a drain current of 6.04 A at a drain voltage of 2 V, a BV of 520 V at a drain leakage current of $250{\mu}A$, and an on-resistance of $331m{\Omega}$. Finally, a boost converter is used to evaluate the performance of the cascode GaN FET in power conversion applications.