• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1109-1114
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• 2003

In this paper, task control architecture is proposed for a mobile robot with behaviors based on cognition theory to endow the robot intelligence. In the task control architecture, task manager is introduced especially for the management of computational resource. The management is based on classical RMS (Rate Monotonic Strategy), but with online rate modulation strategy. The rate modulation is performed using the value variances of behavior execution for the task. Because the values are based on natively uncertain sensor information, they are modeled using PDF (probability Density Function). As a rate modulation process, the range of the rate modulation is defined firstly by real-time constraints of RMS and discrete control stability of behaviors. With the allowable range, rate modulations are performed considering harmonic bases to maintain utilization bound without decrease. To evaluate the efficiency of the proposed rate modulation strategy, a simulation test is performed to compare the efficiency between the control architecture with the proposed strategy and previous one. A performance index with the formalization of propensity of resource allocation is proposed and utilized for the simulation test. To evaluate the appropriateness of the performance index, the performance index is compared with practical one through a practical simulation test.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.5
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• pp.232-242
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• 2005

This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in BFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can be mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated.